Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12272688 | Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap | Leonard P. GULER, Glenn A. Glass, Szuya S. Liao | 2025-04-08 |
| 12206027 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Glenn A. Glass, Anand S. Murthy, Biswajeet Guha, Tahir Ghani, Susmita Ghose | 2025-01-21 |
| 11996404 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady +5 more | 2024-05-28 |
| 11978784 | Gate-all-around integrated circuit structures having germanium nanowire channel structures | Cory Bomberger, Anand S. Murthy, Susmita Ghose | 2024-05-07 |
| 11769836 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Glenn A. Glass, Anand S. Murthy, Biswajeet Guha, Tahir Ghani, Susmita Ghose | 2023-09-26 |
| 11532734 | Gate-all-around integrated circuit structures having germanium nanowire channel structures | Cory Bomberger, Anand S. Murthy, Susmita Ghose | 2022-12-20 |
| 11244943 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady +5 more | 2022-02-08 |