Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure

Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure

US Patent 12369399 · Granted Jul 22, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Nanowire transistor fabrication with hardmask layers2025
Vertically spaced intra-level interconnect line metallization for integrated cir2025
Gate-to-gate isolation for stacked transistor architecture via non-selective die2025
Gate-to-gate isolation for stacked transistor architecture via non-selective die2025
Trench-based quantum dot devices with conductive liners2025
Plug and recess process for dual metal gate on stacked nanoribbon devices2025
Plug and recess process for dual metal gate on stacked nanoribbon devices2025
Conductive contacts wrapped around epitaxial source or drain regions2025
SRAM with P-type access transistors and complementary field-effect transistor te2025
Co-deposition of titanium and silicon for improved silicon germanium source and 2025
Compositional engineering of Schottky diode2025
Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor 2025