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USPTO Patent Rankings Data through Dec 31, 2025
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Peter G. Tolchinsky — 28 Patents

Intel: 28 patents #1,370 of 30,777Top 5%
SASiltronic Ag: 1 patents #145 of 300Top 50%
Beaverton, OR: #206 of 3,140 inventorsTop 7%
Oregon: #1,435 of 28,073 inventorsTop 6%
Overall (All Time): #134,628 of 4,157,543Top 4%
28 Patents All Time
Peter G. Tolchinsky has been granted 28 US patents while listed as an inventor at Intel. The first was granted in 2005 and the most recent in December 2020. Peter G. Tolchinsky ranks #134,628 of 4,157,543 US inventors in our database (top 3.2%). Patent records list Peter G. Tolchinsky in Beaverton, OR, US.

Issued Patents All Time

Showing 1–25 of 28 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10879134 Techniques for monolithic co-integration of silicon and III-N semiconductor transistors Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta 2020-12-29 $24,597,000
10692839 GaN devices on engineered silicon substrates Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Robert S. Chau 2020-06-23 $27,746,000
10600787 Silicon PMOS with gallium nitride NMOS for voltage regulation Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Roza Kotlyar, Valluri Rao 2020-03-24 $21,125,000
9711591 Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby Niloy Mukherjee, Matthew V. Metz, James M. Powers, Van H. Le, Benjamin Chu-Kung +6 more 2017-07-18 $6,909,000
9691843 Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition Annalisa Cappellani, Kelin J. Kuhn, Glenn A. Glass, Van H. Le 2017-06-27 $7,334,000
9691632 Epitaxial wafer and a method of manufacturing thereof Peter Storck, Norbert Werner, Martin Vorderwestner, Irwin Yablok 2017-06-27
9559160 Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition Annalisa Cappellani, Kelin J. Kuhn, Glenn A. Glass, Van H. Le 2017-01-31 $9,360,000
8617945 Stacking fault and twin blocking barrier for integrating III-V on Si Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Joel M. Fastenau, Dmitri Loubychev +1 more 2013-12-31 $14,080,000
8217383 High hole mobility p-channel Ge transistor structure on Si substrate Mantu K. Hudait, Suman Datta, Jack T. Kavalieros 2012-07-10 $16,128,000
8143646 Stacking fault and twin blocking barrier for integrating III-V on Si Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Joel M. Fastenau, Dmitri Loubychev +1 more 2012-03-27 $20,416,000
7863710 Dislocation removal from a group III-V film grown on a semiconductor substrate Mantu K. Hudait, Jack T. Kavalieros, Marko Radosavljevic 2011-01-04 $17,767,000
7851781 Buffer layers for device isolation of devices grown on silicon Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Joel M. Fastenau, Dmitri Loubychev +1 more 2010-12-14 $13,117,000
7791063 High hole mobility p-channel Ge transistor structure on Si substrate Mantu K. Hudait, Suman Datta, Jack T. Kavalieros 2010-09-07 $9,640,000
7687799 Methods of forming buffer layer architecture on silicon and structures formed thereby Mantu K. Hudait, Loren A. Chow, Dmitri Loubychev, Joel M. Fastenau, Amy W. K. Liu 2010-03-30 $14,203,000
7670928 Ultra-thin oxide bonding for S1 to S1 dual orientation bonding Mohamad A. Shaheen, Willy Rachmady 2010-03-02 $14,883,000
7573059 Dislocation-free InSb quantum well structure on Si using novel buffer architecture Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Dmitri Loubychev, Joel M. Fastenau +1 more 2009-08-11 $32,202,000
7569857 Dual crystal orientation circuit devices on the same substrate Mohamad A. Shaheen, Jack T. Kavalieros, Brian S. Doyle, Suman Datta 2009-08-04 $15,097,000
7531429 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices Irwin Yablok, Chuan Hu, Richard Emery 2009-05-12 $14,965,000
7494911 Buffer layers for device isolation of devices grown on silicon Mantu K. Hudait, Mohamad A. Shaheen, Loren A. Chow, Joel M. Fastenau, Dmitri Loubychev +1 more 2009-02-24 $15,365,000
7491988 Transistors with increased mobility in the channel zone and method of fabrication Mark Bohr, Irwin Yablok 2009-02-17 $14,413,000
7473614 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer Martin D. Giles, Michael L. McSwiney, Mohamad A. Shaheen, Irwin Yablok 2009-01-06 $21,219,000
7378331 Methods of vertically stacking wafers using porous silicon Mohamad A. Shaheen, Irwin Yablok, Scott R. List 2008-05-27 $24,811,000
7161224 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process Mohamad A. Shaheen, Ryan Lei, Irwin Yablok 2007-01-09 $12,865,000
7091108 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices Irwin Yablok, Chuan Hu, Richard Emery 2006-08-15 $13,533,000
7042009 High mobility tri-gate devices and methods of fabrication Mohamad A. Shaheen, Brian S. Doyle, Suman Dutta, Robert S. Chau 2006-05-09 $14,660,000