MS

Mohamad A. Shaheen

IN Intel: 25 patents #1,576 of 30,777Top 6%
SO Soitec: 2 patents #91 of 259Top 40%
Overall (All Time): #147,273 of 4,157,543Top 4%
27
Patents All Time

Issued Patents All Time

Showing 25 most recent of 27 patents

Patent #TitleCo-InventorsDate
8735946 Substrate having a charged zone in an insulating buried layer Frédéric Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry +1 more 2014-05-27
8617945 Stacking fault and twin blocking barrier for integrating III-V on Si Mantu K. Hudait, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev +1 more 2013-12-31
8535996 Substrate having a charged zone in an insulating buried layer Frédéric Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry +1 more 2013-09-17
8143646 Stacking fault and twin blocking barrier for integrating III-V on Si Mantu K. Hudait, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev +1 more 2012-03-27
8084818 High mobility tri-gate devices and methods of fabrication Brian S. Doyle, Suman Dutta, Robert S. Chau, Peter Tolchinksy 2011-12-27
8034675 Semiconductor buffer architecture for III-V devices on silicon substrates Mantu K. Hudait, Dmitri Loubychev, Amy W. K. Liu, Joel M. Fastenau 2011-10-11
7851780 Semiconductor buffer architecture for III-V devices on silicon substrates Mantu K. Hudait, Dmitri Loubychev, Amy W. K. Liu, Joel M. Fastenau 2010-12-14
7851781 Buffer layers for device isolation of devices grown on silicon Mantu K. Hudait, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev +1 more 2010-12-14
7723749 Strained semiconductor structures 2010-05-25
7670928 Ultra-thin oxide bonding for S1 to S1 dual orientation bonding Willy Rachmady, Peter G. Tolchinsky 2010-03-02
7573059 Dislocation-free InSb quantum well structure on Si using novel buffer architecture Mantu K. Hudait, Loren A. Chow, Peter G. Tolchinsky, Dmitri Loubychev, Joel M. Fastenau +1 more 2009-08-11
7569857 Dual crystal orientation circuit devices on the same substrate Jack T. Kavalieros, Brian S. Doyle, Suman Datta, Peter G. Tolchinsky 2009-08-04
7494911 Buffer layers for device isolation of devices grown on silicon Mantu K. Hudait, Loren A. Chow, Peter G. Tolchinsky, Joel M. Fastenau, Dmitri Loubychev +1 more 2009-02-24
7473614 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Irwin Yablok 2009-01-06
7378331 Methods of vertically stacking wafers using porous silicon Peter G. Tolchinsky, Irwin Yablok, Scott R. List 2008-05-27
7355247 Silicon on diamond-like carbon devices Kramadhati V. Ravi 2008-04-08
7279369 Germanium on insulator fabrication via epitaxial germanium bonding Ryan Lei 2007-10-09
7202503 III-V and II-VI compounds as template materials for growing germanium containing film on silicon Loren A. Chow 2007-04-10
7161224 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process Peter G. Tolchinsky, Ryan Lei, Irwin Yablok 2007-01-09
7157379 Strained semiconductor structures 2007-01-02
7148122 Bonding of substrates Ryan Lei, Maxim Kelman 2006-12-12
7052978 Arrangements incorporating laser-induced cleaving Mark Liu, Mitchell Taylor 2006-05-30
7042009 High mobility tri-gate devices and methods of fabrication Brian S. Doyle, Suman Dutta, Robert S. Chau, Peter G. Tolchinsky 2006-05-09
6911380 Method of forming silicon on insulator wafers Peter G. Tolchinsky, Irwin Yablok 2005-06-28
6908027 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process Peter G. Tolchinsky, Ryan Lei, Irwin Yablok 2005-06-21