Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8912818 | High speed multiple memory interface I/O cell | Dharmesh Bhakta, Hong-Him Lim, Todd A. Randazzo | 2014-12-16 |
| 8819354 | Feedback programmable data strobe enable architecture for DDR memory applications | Hui-Yin Seto, Derrick Sai-Tang Butt | 2014-08-26 |
| 8743634 | Generic low power strobe based system and method for interfacing memory controller and source synchronous memory | Terence J. Magee | 2014-06-03 |
| 8516425 | Method and computer program for generating grounded shielding wires for signal wiring | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Hui-Yin Seto +5 more | 2013-08-20 |
| 8453096 | Non-linear common coarse delay system and method for delaying data strobe | Terence J. Magee, Christopher Paulson | 2013-05-28 |
| 8324927 | High speed multiple memory interface I/O cell | Dharmesh Bhakta, Hong-Him Lim, Todd A. Randazzo | 2012-12-04 |
| 8235095 | Heat dissipation device | — | 2012-08-07 |
| 8239813 | Method and apparatus for balancing signal delay skew | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Hui-Yin Seto +5 more | 2012-08-07 |
| 8230143 | Memory interface architecture for maximizing access timing margin | Hui-Yin Seto | 2012-07-24 |
| 8059410 | Heat dissipation device | Chun-Chi Chen, Hong-Cheng Yang, Wei-Cheng Nie | 2011-11-15 |
| 7996804 | Signal delay skew reduction system | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Hui-Yin Seto +5 more | 2011-08-09 |
| 7969799 | Multiple memory standard physical layer macro function | Derrick Sai-Tang Butt, Terence J. Magee, Thomas Hughes | 2011-06-28 |
| 7876123 | High speed multiple memory interface I/O cell | Dharmesh Bhakta, Hong-Him Lim, Todd A. Randazzo | 2011-01-25 |
| 7869212 | Heat dissipation device | Hong-Cheng Yang | 2011-01-11 |
| 7865661 | Configurable high-speed memory interface subsystem | Derrick Sai-Tang Butt, Terence J. Magee | 2011-01-04 |
| 7839716 | Apparatus and systems for VT invariant DDR3 SDRAM write leveling | Thomas Hughes | 2010-11-23 |
| 7571396 | System and method for providing swap path voltage and temperature compensation | Thomas Hughes | 2009-08-04 |
| 7454303 | System and method for compensating for PVT variation effects on the delay line of a clock signal | Terence J. Magee, Thomas Hughes | 2008-11-18 |
| 7437500 | Configurable high-speed memory interface subsystem | Derrick Sai-Tang Butt, Terence J. Magee | 2008-10-14 |
| 7239170 | Apparatus and methods for improved input/output cells | Victor Suen, William Lau, Hong-Him Lim | 2007-07-03 |
| 7119596 | Wide-range programmable delay line | Victor Suen | 2006-10-10 |
| 5450455 | Method and apparatus for including the states of nonscannable parts in a scan chain | Stephen W. Hamilton, Walter E. Gibson | 1995-09-12 |
| 5396505 | Programmable error-checking matrix for digital communication system | Jon C. Freeman | 1995-03-07 |
| 4926323 | Streamlined instruction processor | Gigy Baror, Brian W. Case, Rod G. Fleck, Philip M. Freidin, Smeeta Gupta +4 more | 1990-05-15 |
| 4777587 | System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses | Brian W. Case, Rod G. Fleck, Ole H. Moller | 1988-10-11 |