Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8761916 | High-performance tone detection using a digital signal processor (DSP) having multiple arithmetic logic units (ALUs) | Aleksey Alexandrovich Letunovskiy, Ilya Lyalin, Alexander Markovic, Ivan Leonidovich Mazurenko | 2014-06-24 |
| 8677306 | Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC | Alexander E. Andreev, Marian Serbian, Massimo Verita | 2014-03-18 |
| 8566769 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Ranko Scepanovic, Igor Vikhliantsev | 2013-10-22 |
| 8516425 | Method and computer program for generating grounded shielding wires for signal wiring | Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto +5 more | 2013-08-20 |
| 8515055 | Adaptive filtering with flexible selection of algorithm complexity and performance | Ivan Leonidovich Mazurenko, Stanislav V. Aleshin, Dmitry Nikolaevich Babin, Ilya Lyalin, Denis Vassilevich Parfenov | 2013-08-20 |
| 8452006 | Cryptographic processing using a processor | Dmitriy Vladimirovich Alekseev, Alexei V. Galatenko, Aleksey Alexandrovich Letunovskiy, Alexander Markovic | 2013-05-28 |
| 8245168 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Ranko Scepanovic, Igor Vikhliantsev | 2012-08-14 |
| 8239813 | Method and apparatus for balancing signal delay skew | Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto +5 more | 2012-08-07 |
| 8037432 | Method and apparatus for mapping design memories to integrated circuit layout | Alexandre Andreev, Ilya V. Neznanov, Ranko Scepanovic | 2011-10-11 |
| 8006209 | Method and system for outputting a sequence of commands and data described by a flowchart | Alexander E. Andreev, Ranko Scepanovic | 2011-08-23 |
| 7996804 | Signal delay skew reduction system | Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto +5 more | 2011-08-09 |
| 7822099 | Digital Gaussian noise simulator | Alexander E. Andreev, Igor Vikhliantsev | 2010-10-26 |
| 7584442 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Ranko Scepanovic, Igor Vikhliantsev | 2009-09-01 |
| 7512918 | Multimode delay analysis for simplifying integrated circuit design timing models | Alexander E. Andreev, Ranko Scepanovic | 2009-03-31 |
| 7472358 | Method and system for outputting a sequence of commands and data described by a flowchart | Alexander E. Andreev, Ranko Scepanovic | 2008-12-30 |
| 7424687 | Method and apparatus for mapping design memories to integrated circuit layout | Alexandre Andreev, Ilya V. Neznanov, Ranko Scepanovic | 2008-09-09 |
| 7415691 | Method and system for outputting a sequence of commands and data described by a flowchart | Alexander E. Andreev, Ranko Scepanovic | 2008-08-19 |
| 7404166 | Method and system for mapping netlist of integrated circuit to design | Alexander E. Andreev, Pavel A. Panteleev | 2008-07-22 |
| 7389484 | Method and apparatus for tiling memories in integrated circuit layout | Alexandre Andreev, Ilya V. Neznanov, Ranko Scepanovic | 2008-06-17 |
| 7380223 | Method and system for converting netlist of integrated circuit between libraries | Pavel A. Panteleev, Alexander E. Andreev | 2008-05-27 |
| 7356743 | RRAM controller built in self test memory | Ilya V. Neznanov, Alexander E. Andreev | 2008-04-08 |
| 7328423 | Method for evaluating logic functions by logic circuits having optimized number of and/or switches | Alexander E. Andreev | 2008-02-05 |
| 7315993 | Verification of RRAM tiling netlist | Alexander E. Andreev, Ranko Scepanovic | 2008-01-01 |
| 7263470 | Digital gaussian noise simulator | Alexander E. Andreev, Igor Vikhliantsev | 2007-08-28 |
| 7257807 | Method for optimizing execution time of parallel processor programs | Alexander E. Andreev | 2007-08-14 |