Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9024657 | Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller | Alexander E. Andreev, Ranko Scepanovic, Ivan Pavisic, Alexander Yahontov, Mikhail Udovikhin +3 more | 2015-05-05 |
| 8566769 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Andrey Nikitin, Ranko Scepanovic | 2013-10-22 |
| 8347167 | Circuits for implementing parity computation in a parallel architecture LDPC decoder | Alexander E. Andreev, Vojislav Vukovie | 2013-01-01 |
| 8245168 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Andrey Nikitin, Ranko Scepanovic | 2012-08-14 |
| 8151160 | Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same | Alexander E. Andreev | 2012-04-03 |
| 8035537 | Methods and apparatus for programmable decoding of a plurality of code types | Alexander E. Andreev, Sergey Gribok, Oleg Izyumin, Ranko Scepanovic, Vojislav Vukovic | 2011-10-11 |
| 7934139 | Parallel LDPC decoder | Alexander E. Andreev, Sergey Gribok | 2011-04-26 |
| 7913149 | Low complexity LDPC encoding algorithm | Sergey Gribok, Alexander E. Andreev | 2011-03-22 |
| 7822099 | Digital Gaussian noise simulator | Andrey Nikitin, Alexander E. Andreev | 2010-10-26 |
| 7739471 | High performance tiling for RRAM memory | Alexander E. Andreev, Ranko Scepanovic | 2010-06-15 |
| 7667494 | Methods and apparatus for fast unbalanced pipeline architecture | Alexander E. Andreev, Ivan Pavisic | 2010-02-23 |
| 7584442 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Andrey Nikitin, Ranko Scepanovic | 2009-09-01 |
| 7313660 | Data stream frequency reduction and/or phase shift | Alexander E. Andreev, Vojislav Vukovic | 2007-12-25 |
| 7263470 | Digital gaussian noise simulator | Andrey Nikitin, Alexander E. Andreev | 2007-08-28 |
| 7210113 | Process and apparatus for placing cells in an IC floorplan | Alexander E. Andreev, Andrey Nikitin | 2007-04-24 |
| 7207026 | Memory tiling architecture | Alexandre Andreev, Ivan Pavisic | 2007-04-17 |
| 7155688 | Memory generation and placement | Alexandre Andreev, Ilya V. Neznanov, Andrey Nikitin, Ranko Scepanovic | 2006-12-26 |
| 7072922 | Integrated circuit and process for identifying minimum or maximum input value among plural inputs | Alexander E. Andreev, Anatoli Bolotov | 2006-07-04 |
| 7065606 | Controller architecture for memory mapping | Alexander E. Andreev, Ranko Scepanovic | 2006-06-20 |
| 7062726 | Method for generating tech-library for logic function | Alexander E. Andreev, Anatoli Bolotov | 2006-06-13 |
| 7050582 | Pseudo-random one-to-one circuit synthesis | Alexander E. Andreev, Ranko Scepanovic | 2006-05-23 |
| 7036102 | Process and apparatus for placement of cells in an IC during floorplan creation | Alexander E. Andreev, Andrey Nikitin | 2006-04-25 |
| 6941533 | Clock tree synthesis with skew for memory devices | Alexander E. Andreev, Ivan Pavisic | 2005-09-06 |
| 6941494 | Built-in test for multiple memory circuits | Alexander E. Andreev, Lav D. Ivanovic | 2005-09-06 |
| 6848094 | Netlist redundancy detection and global simplification | Alexander E. Andreev | 2005-01-25 |