Issued Patents All Time
Showing 25 most recent of 177 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9239704 | Variable node processing unit | Sergey Gribok, Oleg Izyumin | 2016-01-19 |
| 9024657 | Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller | Ranko Scepanovic, Ivan Pavisic, Alexander Yahontov, Mikhail Udovikhin, Igor Vikhliantsev +3 more | 2015-05-05 |
| 8957398 | Via-configurable high-performance logic block involving transistor chains | Sergey Gribok, Ranko Scepanovic, Phey-Chuin Tan, Chee-Wei Kung | 2015-02-17 |
| 8769372 | System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units | Sergey Gribok, Vojislav Vukovic | 2014-07-01 |
| 8735857 | Via-configurable high-performance logic block architecture | Sergey Gribok, Ranko Scepanovic | 2014-05-27 |
| 8677306 | Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC | Andrey Nikitin, Marian Serbian, Massimo Verita | 2014-03-18 |
| 8629548 | Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node | Andrey V. Nikishin, Sergey Gribok, Phey-Chuin Tan, Choon-Hun Choo | 2014-01-14 |
| 8527851 | System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors | Elyar E. Gasanov, Pavel A. Aliseychik, Ilya V. Neznanov, Pavel A. Panteleev | 2013-09-03 |
| 8443033 | Variable node processing unit | Sergey Gribok, Oleg Izyumin | 2013-05-14 |
| 8347167 | Circuits for implementing parity computation in a parallel architecture LDPC decoder | Vojislav Vukovie, Igor Vikhliantsev | 2013-01-01 |
| 8286060 | Scheme for erasure locator polynomial calculation in error-and-erasure decoder | Pavel A. Panteleev, Elyar E. Gasanov, Ilya V. Neznanov, Pavel A. Aliseychik | 2012-10-09 |
| 8250129 | Cryptographic random number generator using finite field operations | Sergey Gribok, Sergey B. Gashkov | 2012-08-21 |
| 8181096 | Configurable Reed-Solomon decoder based on modified Forney syndromes | Ilya V. Neznanov, Elyar E. Gasanov, Pavel A. Panteleev | 2012-05-15 |
| 8151160 | Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same | Igor Vikhliantsev | 2012-04-03 |
| 8132075 | Memory mapping for parallel turbo decoding | Anatoli Bolotov, Ranko Scepanovic | 2012-03-06 |
| 8095845 | System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units | Sergey Gribok, Vojislav Vukovic | 2012-01-10 |
| 8035537 | Methods and apparatus for programmable decoding of a plurality of code types | Sergey Gribok, Oleg Izyumin, Ranko Scepanovic, Igor Vikhliantsev, Vojislav Vukovic | 2011-10-11 |
| 8006209 | Method and system for outputting a sequence of commands and data described by a flowchart | Andrey Nikitin, Ranko Scepanovic | 2011-08-23 |
| 7934139 | Parallel LDPC decoder | Igor Vikhliantsev, Sergey Gribok | 2011-04-26 |
| 7913149 | Low complexity LDPC encoding algorithm | Sergey Gribok, Igor Vikhliantsev | 2011-03-22 |
| 7882406 | Built in test controller with a downloadable testing program | Anatoli Bolotov | 2011-02-01 |
| 7877724 | Decision tree representation of a function | Vojislav Vokovic, Ranko Scepanovic | 2011-01-25 |
| 7856577 | Command language for memory testing | Anatoli Bolotov, Ranko Scepanovic | 2010-12-21 |
| 7822099 | Digital Gaussian noise simulator | Andrey Nikitin, Igor Vikhliantsev | 2010-10-26 |
| 7823050 | Low area architecture in BCH decoder | Elyar E. Gasanov, Ilya V. Neznanov, Pavel A. Panteleev, Sergei B. Gashkov | 2010-10-26 |