| 11556692 |
High performance regularized network-on-chip architecture |
Gregg William Baeckler, Martin Langhammer |
2023-01-17 |
| 11467804 |
Geometric synthesis |
Gregg William Baeckler, Martin Langhammer |
2022-10-11 |
| 11436399 |
Method and apparatus for performing multiplier regularization |
Martin Langhammer, Gregg William Baeckler |
2022-09-06 |
| 11334318 |
Prefix network-directed addition |
Martin Langhammer, Bogdan Pasca |
2022-05-17 |
| 11210063 |
Machine learning training architecture for programmable devices |
Martin Langhammer, Bogdan Pasca, Gregg William Baeckler, Andrei Hagiescu |
2021-12-28 |
| 11080019 |
Method and apparatus for performing synthesis for field programmable gate array embedded feature placement |
Martin Langhammer, Gregg William Baeckler |
2021-08-03 |
| 11016733 |
Continuous carry-chain packing |
Martin Langhammer, Gregg William Baeckler |
2021-05-25 |
| 10922471 |
High performance regularized network-on-chip architecture |
Gregg William Baeckler, Martin Langhammer |
2021-02-16 |
| 10871946 |
Methods for using a multiplier to support multiple sub-multiplication operations |
Martin Langhammer, Gregg William Baeckler, Dmitry N. Denisenko, Bogdan Pasca |
2020-12-22 |
| 10867090 |
Method and apparatus for implementing an application aware system on a programmable logic device |
Gregg William Baeckler, Martin Langhammer, Scott J. Weber, Gregory Steinke |
2020-12-15 |
| 10790829 |
Logic circuits with simultaneous dual function capability |
Martin Langhammer, Gregg William Baeckler |
2020-09-29 |
| 10732932 |
Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension |
Bogdan Pasca, Martin Langhammer, Gregg William Baeckler |
2020-08-04 |
| 10715144 |
Logic circuits with augmented arithmetic densities |
Gregg William Baeckler, Martin Langhammer |
2020-07-14 |
| 10102892 |
RAM-based shift register with embedded addressing |
— |
2018-10-16 |
| 9239704 |
Variable node processing unit |
Alexander E. Andreev, Oleg Izyumin |
2016-01-19 |
| 8957398 |
Via-configurable high-performance logic block involving transistor chains |
Alexander E. Andreev, Ranko Scepanovic, Phey-Chuin Tan, Chee-Wei Kung |
2015-02-17 |
| 8735857 |
Via-configurable high-performance logic block architecture |
Alexander E. Andreev, Ranko Scepanovic |
2014-05-27 |
| 8629548 |
Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node |
Alexander E. Andreev, Andrey V. Nikishin, Phey-Chuin Tan, Choon-Hun Choo |
2014-01-14 |
| 8436700 |
MEMS-based switching |
Herman Schmit |
2013-05-07 |
| 7546505 |
Built in self test transport controller architecture |
Alexander E. Andreev, Ivan Pavisic |
2009-06-09 |
| 7430694 |
Memory BISR architecture for a slice |
Alexander E. Andreev, Anatoli Bolotov |
2008-09-30 |
| 7328382 |
Memory BISR controller architecture |
Alexander E. Andreev, Anatoli Bolotov |
2008-02-05 |
| 7308633 |
Master controller architecture |
Alexandre Andreev, Anatoli Bolotov |
2007-12-11 |
| 7283385 |
RRAM communication system |
Alexander E. Andreev, Anatoli Bolotov |
2007-10-16 |
