Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Herman Schmit — 145 Patents

TATabula: 79 patents #3 of 42Top 8%
Intel: 43 patents #801 of 30,777Top 3%
CUCarnegie Mellon University: 6 patents #79 of 1,507Top 6%
EAEasic: 3 patents #9 of 43Top 25%
Google: 1 patents #14,887 of 22,993Top 65%
Palo Alto, CA: #49 of 9,675 inventorsTop 1%
California: #1,067 of 386,348 inventorsTop 1%
Overall (All Time): #6,675 of 4,157,543Top 1%
145 Patents All Time
Herman Schmit has been granted 145 US patents while listed as an inventor at Tabula. The first was granted in 2002 and the most recent in November 2024. Herman Schmit ranks #6,675 of 4,157,543 US inventors in our database (top 0.16%). Patent records list Herman Schmit in Palo Alto, CA, US.

Issued Patents All Time

Showing 1–25 of 145 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12147793 Sharding for synchronous processors Reiner Pope, Michial Allen Gunter 2024-11-19 $89,094,000
11799485 Techniques for reducing uneven aging in integrated circuits 2023-10-24 $20,059,000
11210443 Distributed programmable delay lines in a clock tree 2021-12-28 $27,770,000
11159167 Techniques for reducing uneven aging in integrated circuits 2021-10-26 $21,268,000
11115026 Systems and methods for routing data across regions of an integrated circuit Sean R. Atsatt 2021-09-07 $31,495,000
10860760 Systems and methods for implementing learned parameter systems on a programmable integrated circuit Thiam Khean Hah, Vamsi Nalluri, Scott J. Weber, Randy Renfu Huang 2020-12-08 $30,873,000
10678979 Method and apparatus for implementing a system-level design tool for design planning and architecture exploration Michael D. Hutton 2020-06-09
10587273 Systems and methods for routing data across regions of an integrated circuit Sean R. Atsatt 2020-03-10 $31,328,000
10523207 Programmable circuit having multiple sectors Dana How, Sean R. Atsatt, Michael D. Hutton 2019-12-31
10367745 Network-on-chip with fixed and configurable functions Dana How, Sean R. Atsatt 2019-07-30
10367756 Programmable logic device with integrated network-on-chip Michael D. Hutton, Dana How 2019-07-30
10303834 Regional design-dependent voltage control and clocking David Lewis 2019-05-28 $17,387,000
10289483 Methods and apparatus for embedding an error correction code in storage circuits Michael D. Hutton 2019-05-14
10191661 Lutram dummy read scheme during error detection and correction Bee Yee Ng, Gaik Ming Chan, Jeffrey Christopher Chromczak 2019-01-29
10187064 Systems and methods for routing data across regions of an integrated circuit Sean R. Atsatt 2019-01-22 $27,645,000
10141936 Pipelined interconnect circuitry with double data rate interconnections David Lewis, Carl Ebeling 2018-11-27
10055526 Regional design-dependent voltage control and clocking David Lewis 2018-08-21 $25,621,000
10044344 Systems and methods for a low hold-time sequential input stage Dana How 2018-08-07
9946826 Circuit design implementations in secure partitions of an integrated circuit Sean R. Atsatt, Ting Lu, Dana How 2018-04-17
9922157 Sector-based clock routing methods and apparatus Carl Ebeling, Dana How, Mahesh A. Iyer, Saurabh Adya 2018-03-20
9813061 Circuitry for implementing multi-mode redundancy and arithmetic functions David Lewis 2017-11-07
9806696 Systems and methods for a low hold-time sequential input stage Dana How 2017-10-31
9768783 Methods for operating configurable storage and processing blocks at double and single data rates Jiefan Zhang 2017-09-19
9755647 Techniques for handling high voltage circuitry in an integrated circuit Andy L. Lee 2017-09-05
9740808 Method and apparatus for implementing a system-level design tool for design planning and architecture exploration Michael D. Hutton 2017-08-22