Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
CE

Carl Ebeling — 17 Patents

Intel: 15 patents #2,763 of 30,777Top 9%
BUBar-Ilan University: 1 patents #152 of 412Top 40%
MCMeta Systems Co.: 1 patents #6 of 11Top 55%
UUUniversity Of Utah: 1 patents #787 of 1,848Top 45%
Redwood City, CA: #578 of 5,061 inventorsTop 15%
California: #35,467 of 386,348 inventorsTop 10%
Overall (All Time): #263,971 of 4,157,543Top 7%
17 Patents All Time
Carl Ebeling has been granted 17 US patents while listed as an inventor at Intel. The first was granted in 2011 and the most recent in February 2022. Carl Ebeling ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Carl Ebeling in Redwood City, CA, US.

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11256979 Common factor mass multiplication circuitry Thiam Khean Hah, Vamsi Nalluri 2022-02-22 $16,582,000
10853034 Common factor mass multiplication circuitry Thiam Khean Hah, Jason Gee Hock Ong, Yeong Tat Liew, Vamsi Nalluri 2020-12-01 $25,476,000
10585272 Coherent fluorescence super-resolution microscopy Rajesh Menon, Jordan M. Gerton, Amihai MEIRI, Zeev Zalevsky 2020-03-10
10523224 Techniques for signal skew compensation David W. Mendel, Dana How, Mahesh A. Iyer 2019-12-31
10423747 Method and apparatus for supporting temporal virtualization on a target device Scott J. Weber 2019-09-24 $28,939,000
10333535 Techniques for signal skew compensation David W. Mendel, Dana How, Mahesh A. Iyer 2019-06-25
10141936 Pipelined interconnect circuitry with double data rate interconnections David Lewis, Herman Schmit 2018-11-27
10074409 Configurable storage blocks having simple first-in first-out enabling circuitry Simon Finn 2018-09-11 $19,778,000
9960903 Systems and methods for clock alignment using pipeline stages Dana How, Audrey Kertesz 2018-05-01
9922157 Sector-based clock routing methods and apparatus Herman Schmit, Dana How, Mahesh A. Iyer, Saurabh Adya 2018-03-20
9824024 Configurable storage blocks with embedded first-in first-out and delay line circuitry Jeffrey Christopher Chromczak, David Lewis 2017-11-21
9692418 Pipelined interconnect circuitry with double data rate interconnections David Lewis, Herman Schmit 2017-06-27
9606573 Configurable clock grid structures Dana How, Herman Schmit, Vadim Gutnik, Ramanand Venkata 2017-03-28
9558796 Systems and methods for maintaining memory access coherency in embedded memory blocks Pohrong Rita Chu 2017-01-31
9501092 Systems and methods for clock alignment using pipeline stages Dana How, Audrey Kertesz 2016-11-22
9218862 Method and apparatus for operating finite-state machines in configurable storage circuits Richard A. Grenier 2015-12-22 $45,091,000
8003906 Crossbar device constructed with MEMS switches Frederic Reblewski, Olivier LePape, Jean Barbier 2011-08-23