Issued Patents All Time
Showing 25 most recent of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11749368 | Quick configurable universal register for a configurable integrated circuit die | Bee Yee Ng | 2023-09-05 |
| 10591544 | Programmable integrated circuits with in-operation reconfiguration capability | Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz | 2020-03-17 |
| 10523224 | Techniques for signal skew compensation | David W. Mendel, Carl Ebeling, Mahesh A. Iyer | 2019-12-31 |
| 10523207 | Programmable circuit having multiple sectors | Sean R. Atsatt, Michael D. Hutton, Herman Schmit | 2019-12-31 |
| 10367745 | Network-on-chip with fixed and configurable functions | Herman Schmit, Sean R. Atsatt | 2019-07-30 |
| 10367756 | Programmable logic device with integrated network-on-chip | Michael D. Hutton, Herman Schmit | 2019-07-30 |
| 10333535 | Techniques for signal skew compensation | David W. Mendel, Carl Ebeling, Mahesh A. Iyer | 2019-06-25 |
| 10210919 | Integrated circuits with embedded double-clocked components | Martin Langhammer | 2019-02-19 |
| 10082541 | Mixed redundancy scheme for inter-die interconnects in a multichip package | Dinesh Patil, Arifur Rahman, Jeffrey Erik Schulz | 2018-09-25 |
| 10044344 | Systems and methods for a low hold-time sequential input stage | Herman Schmit | 2018-08-07 |
| 9960903 | Systems and methods for clock alignment using pipeline stages | Carl Ebeling, Audrey Kertesz | 2018-05-01 |
| 9946826 | Circuit design implementations in secure partitions of an integrated circuit | Sean R. Atsatt, Ting Lu, Herman Schmit | 2018-04-17 |
| 9922157 | Sector-based clock routing methods and apparatus | Carl Ebeling, Herman Schmit, Mahesh A. Iyer, Saurabh Adya | 2018-03-20 |
| 9843332 | Clock grid for integrated circuit | Ramanand Venkata, Christopher F. Lane | 2017-12-12 |
| 9806696 | Systems and methods for a low hold-time sequential input stage | Herman Schmit | 2017-10-31 |
| 9703526 | Self-stuffing multi-clock FIFO requiring no synchronizers | — | 2017-07-11 |
| 9698784 | Level-sensitive two-phase single-wire latch controllers without contention | — | 2017-07-04 |
| 9685957 | System reset controller replacing individual asynchronous resets | — | 2017-06-20 |
| 9665677 | Memory controller for heterogeneous configurable integrated circuit | Suresh Subramanian, Mukunda Krishnappa, Pohrong Rita Chu, Jason Golbus | 2017-05-30 |
| 9660630 | Clock grid for integrated circuit | Ramanand Venkata, Christopher F. Lane | 2017-05-23 |
| 9606573 | Configurable clock grid structures | Carl Ebeling, Herman Schmit, Vadim Gutnik, Ramanand Venkata | 2017-03-28 |
| 9602587 | Multiple plane network-on-chip with master/slave inter-relationships | — | 2017-03-21 |
| 9588176 | Techniques for using scan storage circuits | Michael D. Hutton, Sean R. Atsatt, James Ball, Jeffrey Christopher Chromczak, Eng Ling Ho | 2017-03-07 |
| 9553762 | Network-on-chip with fixed and configurable functions | Herman Schmit, Sean R. Atsatt | 2017-01-24 |
| 9501092 | Systems and methods for clock alignment using pipeline stages | Carl Ebeling, Audrey Kertesz | 2016-11-22 |