Issued Patents All Time
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10649944 | Configuration via high speed serial link | Gopi Krishnamurthy | 2020-05-12 |
| 9843332 | Clock grid for integrated circuit | Dana How, Christopher F. Lane | 2017-12-12 |
| 9690741 | Configuration via high speed serial link | Gopi Krishnamurthy | 2017-06-27 |
| 9660630 | Clock grid for integrated circuit | Dana How, Christopher F. Lane | 2017-05-23 |
| 9606573 | Configurable clock grid structures | Carl Ebeling, Dana How, Herman Schmit, Vadim Gutnik | 2017-03-28 |
| 9515880 | Integrated circuits with clock selection circuitry | Henry Y. Lui, Victor Maruri, David W. Mendel, Andrew Bellis | 2016-12-06 |
| 9503057 | Clock grid for integrated circuit | Dana How, Christopher F. Lane | 2016-11-22 |
| 9438272 | Digital phase locked loop circuitry and methods | Chong H. Lee | 2016-09-06 |
| 9077341 | Programmable matrix for the allocation of communication resources | Catherine Chang, Henry Liu | 2015-07-07 |
| 9077330 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang +1 more | 2015-07-07 |
| 9024673 | Techniques for providing clock signals in an integrated circuit | Ryan Fung, Ketan Zaveri | 2015-05-05 |
| 8994425 | Techniques for aligning and reducing skew in serial data signals | Henry Y. Lui, Arch Zaliznyak | 2015-03-31 |
| 8923440 | Circuitry for padded communication protocols | Binh Ton | 2014-12-30 |
| 8812893 | Apparatus and methods for low-skew channel bonding | Henry Y. Lui | 2014-08-19 |
| 8804890 | Digital phase locked loop circuitry and methods | Chong H. Lee | 2014-08-12 |
| 8692595 | Transceiver circuitry with multiple phase-locked loops | David W. Mendel, Sergey Shumarayev | 2014-04-08 |
| 8581653 | Techniques for providing clock signals in clock networks | Victor Maruri, Arch Zaliznyak, Henry Y. Lui | 2013-11-12 |
| 8570197 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang +1 more | 2013-10-29 |
| 8571059 | Apparatus and methods for serial interfaces with shared datapaths | Arch Zaliznyak, Surinder Singh, Henry Y. Lui, Tim Tri Hoang, Sergey Shumarayev +1 more | 2013-10-29 |
| 8462908 | Digital phase locked loop circuitry and methods | Chong H. Lee | 2013-06-11 |
| 7869553 | Digital phase locked loop circuitry and methods | Chong H. Lee | 2011-01-11 |
| 7848318 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang +1 more | 2010-12-07 |
| 7698482 | Multiple data rates in integrated circuit device serial interface | Rakesh Patel, Chong H. Lee | 2010-04-13 |
| 7659838 | Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits | Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Tim Tri Hoang +1 more | 2010-02-09 |
| 7656187 | Multi-channel communication circuitry for programmable logic device integrated circuits and the like | Thungoc M. Tran, Sergey Shumarayev, Tim Tri Hoang, Ning Xue, Chong H. Lee | 2010-02-02 |