Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7646217 | Programmable logic device with serial interconnect | Rakesh Patel, Chong H. Lee | 2010-01-12 |
| 7577166 | Programmable logic devices with multi-standard byte synchronization and channel alignment for communication | Chong H. Lee, Rakesh Patel | 2009-08-18 |
| 7538578 | Multiple data rates in programmable logic device serial interface | Chong H. Lee, Rakesh Patel | 2009-05-26 |
| 7443922 | Circuitry for padded communication protocols | Binh Ton | 2008-10-28 |
| 7436210 | Next generation 8B10B architecture | Rakesh Patel, Chong H. Lee | 2008-10-14 |
| 7366267 | Clock data recovery with double edge clocking based phase detector and serializer/deserializer | Chong H. Lee | 2008-04-29 |
| 7362833 | Dynamic special character selection for use in byte alignment circuitry | Vinson Chan, Chong H. Lee, Rakesh Patel | 2008-04-22 |
| 7310399 | Clock signal circuitry for multi-protocol high-speed serial interface circuitry | Chong H. Lee | 2007-12-18 |
| 7305058 | Multi-standard clock rate matching circuitry | Chong H. Lee | 2007-12-04 |
| 7292070 | Programmable PPM detector | Seungmyon Park, Chong H. Lee | 2007-11-06 |
| 7272677 | Multi-channel synchronization for programmable logic device serial interface | Chong H. Lee, Rakesh Patel | 2007-09-18 |
| 7183797 | Next generation 8B10B architecture | Rakesh Patel, Chong H. Lee | 2007-02-27 |
| 7180972 | Clock signal circuitry for multi-protocol high-speed serial interface circuitry | Chong H. Lee | 2007-02-20 |
| 7151470 | Data converter with multiple conversions for padded-protocol interface | Ning Xue, Chong H. Lee, Rakesh Patel | 2006-12-19 |
| 7138837 | Digital phase locked loop circuitry and methods | Chong H. Lee, Henry Y. Lui | 2006-11-21 |
| 7131024 | Multiple transmit data rates in programmable logic device serial interface | Chong H. Lee, Rakesh Patel | 2006-10-31 |
| 7071726 | Selectable dynamic reconfiguration of programmable embedded IP | Vinson Chan, Chong H. Lee, Rakesh Patel, Binh Ton | 2006-07-04 |
| 7046174 | Byte alignment for serial data receiver | Henry Y. Lui, Chong H. Lee, Rakesh Patel, John Lam, Vinson Chan +1 more | 2006-05-16 |
| 7039787 | Byte alignment circuitry | Chong H. Lee | 2006-05-02 |
| 6970117 | Byte alignment for serial data receiver | Henry Y. Lui, Chong H. Lee, Rakesh Patel, John Lam, Vinson Chan +1 more | 2005-11-29 |
| 6963223 | Programmable logic devices with multi-standard byte synchronization and channel alignment for communication | Chong H. Lee, Rakesh Patel | 2005-11-08 |
| 6888376 | Multiple data rates in programmable logic device serial interface | Chong H. Lee, Rakesh Patel | 2005-05-03 |
| 6867616 | Programmable logic device serial interface having dual-use phase-locked loop circuitry | Chong H. Lee, Rakesh Patel | 2005-03-15 |
| 6854044 | Byte alignment circuitry | Chong H. Lee | 2005-02-08 |
| 6842034 | Selectable dynamic reconfiguration of programmable embedded IP | Vinson Chan, Chong H. Lee, Rakesh Patel, Binh Ton | 2005-01-11 |