Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9515880 | Integrated circuits with clock selection circuitry | Ramanand Venkata, Victor Maruri, David W. Mendel, Andrew Bellis | 2016-12-06 |
| 8994425 | Techniques for aligning and reducing skew in serial data signals | Ramanand Venkata, Arch Zaliznyak | 2015-03-31 |
| 8812755 | Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system | Surinder Singh, Wai-Bor Leung, Arch Zaliznyak | 2014-08-19 |
| 8812893 | Apparatus and methods for low-skew channel bonding | Ramanand Venkata | 2014-08-19 |
| 8751551 | Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry | Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis +3 more | 2014-06-10 |
| 8739099 | Method and apparatus for determining clock uncertainties | Victor Maruri, Boon Jin Ang, Surinder Singh, Thow Pang Chong, Tony Ngai | 2014-05-27 |
| 8700825 | Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system | Surinder Singh, Wai-Bor Leung, Arch Zaliznyak | 2014-04-15 |
| 8645450 | Multiplier-accumulator circuitry and methods | Kok Heng Choe, Tony Ngai | 2014-02-04 |
| 8620977 | Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry | Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis +3 more | 2013-12-31 |
| 8581653 | Techniques for providing clock signals in clock networks | Victor Maruri, Arch Zaliznyak, Ramanand Venkata | 2013-11-12 |
| 8571059 | Apparatus and methods for serial interfaces with shared datapaths | Arch Zaliznyak, Ramanand Venkata, Surinder Singh, Tim Tri Hoang, Sergey Shumarayev +1 more | 2013-10-29 |
| 8549055 | Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry | Keone Streicher, Martin Langhammer, Yi-Wen Lin, Wai-Bor Leung, David Lewis +3 more | 2013-10-01 |
| 8307023 | DSP block for implementing large multiplier on a programmable integrated circuit device | Wai-Bor Leung | 2012-11-06 |
| 7684532 | Clock data recovery circuitry associated with programmable logic device circuitry | Edward Aung, Paul Butler, John E. Turner, Rakesh Patel, Chong H. Lee | 2010-03-23 |
| 7570105 | Variable current charge pump with modular switch circuit | Sun Woo Baek, Surinder Singh | 2009-08-04 |
| 7333570 | Clock data recovery circuitry associated with programmable logic device circuitry | Edward Aung, Paul Butler, John E. Turner, Rakesh Patel, Chong H. Lee | 2008-02-19 |
| 7292065 | Enhanced passgate structures for reducing leakage current | Malik Kabani, Rakesh Patel, Tim Tri Hoang | 2007-11-06 |
| 7227918 | Clock data recovery circuitry associated with programmable logic device circuitry | Edward Aung, Paul Butler, John E. Turner, Rakesh Patel, Chong H. Lee | 2007-06-05 |
| 7138837 | Digital phase locked loop circuitry and methods | Ramanand Venkata, Chong H. Lee | 2006-11-21 |
| 7046174 | Byte alignment for serial data receiver | Chong H. Lee, Rakesh Patel, Ramanand Venkata, John Lam, Vinson Chan +1 more | 2006-05-16 |
| 7003423 | Programmable logic resource with data transfer synchronization | Malik Kabani | 2006-02-21 |
| 6985021 | Circuits and techniques for conditioning differential signals | Arch Zaliznyak, William W. Bereza, Chong H. Lee, Rakesh Patel | 2006-01-10 |
| 6970117 | Byte alignment for serial data receiver | Chong H. Lee, Rakesh Patel, Ramanand Venkata, John Lam, Vinson Chan +1 more | 2005-11-29 |
| 6724328 | Byte alignment for serial data receiver | Chong H. Lee, Rakesh Patel, Ramanand Venkata, John Lam, Vinson Chan +1 more | 2004-04-20 |
| 5568081 | Variable slew control for output buffers | Sammy Cheung | 1996-10-22 |