Issued Patents All Time
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10727252 | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same | Scott T. Becker, Carole Lambert | 2020-07-28 |
| 10658385 | Cross-coupled transistor circuit defined on four gate electrode tracks | Scott T. Becker, Carole Lambert | 2020-05-19 |
| 10651200 | Cross-coupled transistor circuit defined on three gate electrode tracks | Scott T. Becker, Carole Lambert | 2020-05-12 |
| 10020321 | Cross-coupled transistor circuit defined on two gate electrode tracks | Scott T. Becker, Carole Lambert | 2018-07-10 |
| 9871056 | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same | Scott T. Becker, Carole Lambert | 2018-01-16 |
| 9536899 | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same | Scott T. Becker, Carole Lambert | 2017-01-03 |
| 9530734 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Stephen Kornachuk, Carole Lambert, Scott T. Becker | 2016-12-27 |
| 9245081 | Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods | Scott T. Becker, Carole Lambert | 2016-01-26 |
| 9213792 | Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods | Scott T. Becker, Carole Lambert | 2015-12-15 |
| 9208279 | Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods | Scott T. Becker, Carole Lambert | 2015-12-08 |
| 9202779 | Enforcement of semiconductor structure regularity for localized transistors and interconnect | Stephen Kornachuk, Carole Lambert, Scott T. Becker | 2015-12-01 |
| 9117050 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications | Scott T. Becker, Carole Lambert | 2015-08-25 |
| 9081931 | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer | Scott T. Becker, Carole Lambert | 2015-07-14 |
| 9009641 | Circuits with linear finfet structures | Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Carole Lambert, Jonathan R. Quandt +1 more | 2015-04-14 |
| 8872283 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature | Scott T. Becker, Carole Lambert | 2014-10-28 |
| 8866197 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature | Scott T. Becker, Carole Lambert | 2014-10-21 |
| 8863063 | Finfet transistor circuit | Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Carole Lambert, Jonathan R. Quandt +1 more | 2014-10-14 |
| 8853794 | Integrated circuit within semiconductor chip including cross-coupled transistor configuration | Scott T. Becker, Carole Lambert | 2014-10-07 |
| 8853793 | Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends | Scott T. Becker, Carole Lambert | 2014-10-07 |
| 8847329 | Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts | Scott T. Becker, Carole Lambert | 2014-09-30 |
| 8847331 | Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures | Scott T. Becker, Carole Lambert | 2014-09-30 |
| 8836045 | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track | Scott T. Becker, Carole Lambert | 2014-09-16 |
| 8835989 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications | Scott T. Becker, Carole Lambert | 2014-09-16 |
| 8816402 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor | Scott T. Becker, Carole Lambert | 2014-08-26 |
| 8785978 | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer | Scott T. Becker, Carole Lambert | 2014-07-22 |