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USPTO Patent Rankings Data through Dec 31, 2025
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Saurabh Adya — 12 Patents

Apple: 5 patents #5,490 of 18,612Top 30%
Intel: 5 patents #7,234 of 30,777Top 25%
SYSynopsys: 2 patents #669 of 2,302Top 30%
San Jose, CA: #5,425 of 32,062 inventorsTop 20%
California: #51,404 of 386,348 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Saurabh Adya has been granted 12 US patents while listed as an inventor at Intel. The first was granted in 2012 and the most recent in October 2025. Saurabh Adya ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Saurabh Adya in San Jose, CA, US.

Patents per Year

Patents granted per year, 2012 to 2025Bar chart with a peak of 3 patents in 2019.peak 32012: 1 patents20122016: 1 patents20162018: 2 patents20182019: 3 patents20192024: 2 patents20242025: 3 patents2025

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12452520 Selectively using sensors for contextual data Myra C. Lukens, Aswath Manoharan, Alkeshkumar M. Patel 2025-10-21
12406664 Multimodal assistant understanding using on-screen and device context Alkeshkumar M. Patel, Karan M. DARYANANI, Myra C. Lukens, Aswath Manoharan 2025-09-02
12190873 Determining whether speech input is intended for a digital assistant Ahmed S. HUSSEN ABDELAZIZ, Alexander W. Churchill, Pranay Dighe, Sachin Kajarekar, Chaitanya Mannemala +6 more 2025-01-07
12073831 Using visual context to improve a virtual assistant Sameer Badaskar, Akanksha Bindal, Ahmed S. HUSSEN ABDELAZIZ, Xiaochuan Niu, Alkeshkumar M. Patel +1 more 2024-08-27 $283,265,000
12027166 Digital assistant reference resolution Hong Yu, Shruti BHARGAVA, Myra C. Lukens, Jianpeng Cheng, Lin Li +3 more 2024-07-02 $221,119,000
10318686 Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graph Shounak Dhar, Mahesh A. Iyer, Love Singhal, Nikolay Rubanov 2019-06-11 $16,707,000
10303202 Method and apparatus for performing clock allocation for a system implemented on a programmable device Mahesh A. Iyer, Love Singhal 2019-05-28
10242144 Methods for minimizing logic overlap on integrated circuits Mahesh A. Iyer, Love Singhal 2019-03-26
10162924 Method and apparatus for performing large scale consensus based clustering Love Singhal, Mahesh A. Iyer 2018-12-25
9922157 Sector-based clock routing methods and apparatus Carl Ebeling, Herman Schmit, Dana How, Mahesh A. Iyer 2018-03-20
9280632 Methods and apparatuses for circuit design and optimization Kenneth S. McElvain, Gael Paul 2016-03-08 $4,348,000
8307315 Methods and apparatuses for circuit design and optimization Kenneth S. McElvain, Gael Paul 2012-11-06 $4,333,000

Frequent Collaborators

Mahesh A. Iyer5 shared
Love Singhal4 shared
Alkeshkumar M. Patel4 shared
Myra C. Lukens3 shared
Srikanth Vishnubhotla2 shared
Ahmed S. HUSSEN ABDELAZIZ2 shared

Nearby-Ranked Inventors

John Patrick Hickey, III12
Gregory Lutter12
Josselin Xavier COUPARD12
Xuan Li12
Nandana Mihindukulasooriya12
Keiichi Matsuda12
Robert Imig12
Peter Mage12
Sze Ping Ching12