Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9024657 | Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller | Alexander E. Andreev, Ranko Scepanovic, Ivan Pavisic, Alexander Yahontov, Mikhail Udovikhin +3 more | 2015-05-05 |
| 8957398 | Via-configurable high-performance logic block involving transistor chains | Alexander E. Andreev, Sergey Gribok, Ranko Scepanovic, Phey-Chuin Tan | 2015-02-17 |