Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9024657 | Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller | Alexander E. Andreev, Ranko Scepanovic, Ivan Pavisic, Mikhail Udovikhin, Igor Vikhliantsev +3 more | 2015-05-05 |