Issued Patents All Time
Showing 25 most recent of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9024657 | Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller | Alexander E. Andreev, Ranko Scepanovic, Alexander Yahontov, Mikhail Udovikhin, Igor Vikhliantsev +3 more | 2015-05-05 |
| 8516425 | Method and computer program for generating grounded shielding wires for signal wiring | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong +5 more | 2013-08-20 |
| 8239813 | Method and apparatus for balancing signal delay skew | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong +5 more | 2012-08-07 |
| 7996804 | Signal delay skew reduction system | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong +5 more | 2011-08-09 |
| 7818703 | Density driven layout for RRAM configuration module | Alexander E. Andreev, Anatoli Bolotov | 2010-10-19 |
| 7667494 | Methods and apparatus for fast unbalanced pipeline architecture | Alexander E. Andreev, Igor Vikhliantsev | 2010-02-23 |
| 7546505 | Built in self test transport controller architecture | Sergey Gribok, Alexander E. Andreev | 2009-06-09 |
| 7356785 | Optimizing IC clock structures by minimizing clock uncertainty | Aiguo Lu, Nikola Radovanovic | 2008-04-08 |
| 7334204 | System for avoiding false path pessimism in estimating net delay for an integrated circuit design | Weiqing Guo, Sandeep Bhutani | 2008-02-19 |
| 7246337 | Density driven layout for RRAM configuration module | Alexander E. Andreev, Anatoli Bolotov | 2007-07-17 |
| 7243324 | Method of buffer insertion to achieve pin specific delays | Aiguo Lu, Nikola Radovanovic | 2007-07-10 |
| 7207026 | Memory tiling architecture | Alexandre Andreev, Igor Vikhliantsev | 2007-04-17 |
| 7194717 | Compact custom layout for RRAM column controller | Alexander E. Andreev, Anatoli Bolotov | 2007-03-20 |
| 7096442 | Optimizing IC clock structures by minimizing clock uncertainty | Aiguo Lu, Nikola Radovanovic | 2006-08-22 |
| 7093228 | Method and system for classifying an integrated circuit for optical proximity correction | Alexandre Andreev, Lav D. Ivanovic | 2006-08-15 |
| 7028274 | RRAM backend flow | Alexander E. Andreev, Ranko Scepanovic, Vojislav Vukovic | 2006-04-11 |
| 6941533 | Clock tree synthesis with skew for memory devices | Alexander E. Andreev, Igor Vikhliantsev | 2005-09-06 |
| 6901571 | Timing-driven placement method utilizing novel interconnect delay model | Dusan Petranovic, Ranko Scepanovic | 2005-05-31 |
| 6810515 | Process of restructuring logics in ICs for setup and hold time optimization | Aiguo Lu, Andrej A. Zolotykh, Elyar E. Gasanov | 2004-10-26 |
| 6804811 | Process for layout of memory matrices in integrated circuits | Alexander E. Andreev, Ranko Scepanovic | 2004-10-12 |
| 6760896 | Process layout of buffer modules in integrated circuits | Alexander E. Andreev, Ranko Scepanovic | 2004-07-06 |
| 6757881 | Power routing with obstacles | Alexandre Andreev, Lav D. Ivanovic | 2004-06-29 |
| 6757877 | System and method for identifying and eliminating bottlenecks in integrated circuit designs | Robert Stenberg | 2004-06-29 |
| 6701493 | Floor plan tester for integrated circuit design | Elyar E. Gasanov, Andrej A. Zolotykh, Aiguo Lu | 2004-03-02 |
| 6637016 | Assignment of cell coordinates | Elyar E. Gasanov, Andrej A. Zolotykh, Aiguo Lu | 2003-10-21 |