Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8160242 | Efficient implementation of arithmetical secure hash techniques | Mikhail I. Grinchuk, Anatoli Bolotov, Lay D. Ivanovic, Alexei V. Galatenko | 2012-04-17 |
| 7568175 | Ramptime propagation on designs with cycles | Elyar E. Gasanov, Alexei V. Galatenko, Ilya Lyalin | 2009-07-28 |
| 7496870 | Method of selecting cells in logic restructuring | Iliya V. Lyalin, Elyar E. Gasanov, Alexei V. Galatenko | 2009-02-24 |
| 7398486 | Method and apparatus for performing logical transformations for global routing | Alexei V. Galatenko, Elyar E. Gasanov | 2008-07-08 |
| 7257791 | Multiple buffer insertion in global routing | Alexei V. Galatenko, Elyar E. Gasanov, Iliya V. Lyalin | 2007-08-14 |
| 7246336 | Ramptime propagation on designs with cycles | Elyar E. Gasanov, Alexei V. Galatenko, Ilya Lyalin | 2007-07-17 |
| 7146591 | Method of selecting cells in logic restructuring | Iliya V. Lyalin, Elyar E. Gasanov, Alexei V. Galatenko | 2006-12-05 |
| 7111267 | Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths | Elyar E. Gasanov, Iliya V. Lyalin, Alexei V. Galatenko | 2006-09-19 |
| 6868536 | Method to find boolean function symmetries | Elyar E. Gasanov, Aiguo Lu | 2005-03-15 |
| 6810515 | Process of restructuring logics in ICs for setup and hold time optimization | Aiguo Lu, Ivan Pavisic, Elyar E. Gasanov | 2004-10-26 |
| 6701493 | Floor plan tester for integrated circuit design | Elyar E. Gasanov, Ivan Pavisic, Aiguo Lu | 2004-03-02 |
| 6701503 | Overlap remover manager | Andrey Nikitin, Elyar E. Gasanov | 2004-03-02 |
| 6681373 | Method and apparatus for dynamic buffer and inverter tree optimization | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2004-01-20 |
| 6651239 | Direct transformation of engineering change orders to synthesized IC chip designs | Andrey Nikitin, Nikola Radovanovic | 2003-11-18 |
| 6637016 | Assignment of cell coordinates | Elyar E. Gasanov, Ivan Pavisic, Aiguo Lu | 2003-10-21 |
| 6637011 | Method and apparatus for quick search for identities applicable to specified formula | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-10-21 |
| 6629304 | Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells | Elyar E. Gasanov, Aiguo Lu, Ivan Pavisic | 2003-09-30 |
| 6564361 | Method and apparatus for timing driven resynthesis | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-05-13 |
| 6553551 | Timing recomputation | Elyar E. Gasanov, Ivan Pavisic, Aiguo Lu | 2003-04-22 |
| 6550044 | Method in integrating clock tree synthesis and timing optimization for an integrated circuit design | Ivan Pavisic, Aiguo Lu, Elyar E. Gasanov | 2003-04-15 |
| 6543032 | Method and apparatus for local resynthesis of logic trees with multiple cost functions | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-04-01 |
| 6532582 | Method and apparatus for optimal critical netlist area selection | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-03-11 |
| 6487697 | Distribution dependent clustering in buffer insertion of high fanout nets | Aiguo Lu, Ivan Pavisic | 2002-11-26 |
| 6470487 | Parallelization of resynthesis | Elyar E. Gasanov, Ivan Pavisic, Aiguo Lu | 2002-10-22 |