Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7496870 | Method of selecting cells in logic restructuring | Andrej A. Zolotykh, Elyar E. Gasanov, Alexei V. Galatenko | 2009-02-24 |
| 7401313 | Method and apparatus for controlling congestion during integrated circuit design resynthesis | Alexei V. Galatenko, Elyar E. Gasanov | 2008-07-15 |
| 7257791 | Multiple buffer insertion in global routing | Alexei V. Galatenko, Elyar E. Gasanov, Andrej A. Zolotykh | 2007-08-14 |
| 7146591 | Method of selecting cells in logic restructuring | Andrej A. Zolotykh, Elyar E. Gasanov, Alexei V. Galatenko | 2006-12-05 |
| 7111267 | Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths | Elyar E. Gasanov, Alexei V. Galatenko, Andrej A. Zolotykh | 2006-09-19 |