Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9460258 | Shaping integrated with power network synthesis (PNS) for power grid (PG) alignment | David L. Peart, Yan Lin, Balkrishna R. Rashingkar, Russell B. Segal, Peiqing Zou | 2016-10-04 |
| 8516425 | Method and computer program for generating grounded shielding wires for signal wiring | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong +5 more | 2013-08-20 |
| 8239813 | Method and apparatus for balancing signal delay skew | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong +5 more | 2012-08-07 |
| 7996804 | Signal delay skew reduction system | Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong +5 more | 2011-08-09 |
| 7356785 | Optimizing IC clock structures by minimizing clock uncertainty | Ivan Pavisic, Nikola Radovanovic | 2008-04-08 |
| 7243324 | Method of buffer insertion to achieve pin specific delays | Ivan Pavisic, Nikola Radovanovic | 2007-07-10 |
| 7096442 | Optimizing IC clock structures by minimizing clock uncertainty | Ivan Pavisic, Nikola Radovanovic | 2006-08-22 |
| 6934733 | Optimization of adder based circuit architecture | Sergej B. Gashkov, Alexander E. Andreev | 2005-08-23 |
| 6868536 | Method to find boolean function symmetries | Elyar E. Gasanov, Andrej A. Zolotykh | 2005-03-15 |
| 6810515 | Process of restructuring logics in ICs for setup and hold time optimization | Ivan Pavisic, Andrej A. Zolotykh, Elyar E. Gasanov | 2004-10-26 |
| 6701493 | Floor plan tester for integrated circuit design | Elyar E. Gasanov, Andrej A. Zolotykh, Ivan Pavisic | 2004-03-02 |
| 6691283 | Optimization of comparator architecture | Sergej B. Gashkov, Alexander E. Andreev | 2004-02-10 |
| 6637016 | Assignment of cell coordinates | Elyar E. Gasanov, Andrej A. Zolotykh, Ivan Pavisic | 2003-10-21 |
| 6629304 | Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells | Elyar E. Gasanov, Andrej A. Zolotykh, Ivan Pavisic | 2003-09-30 |
| 6557144 | Netlist resynthesis program based on physical delay calculation | Ivan Pavisic, Pedja Raspopovic | 2003-04-29 |
| 6553551 | Timing recomputation | Andrej A. Zolotykh, Elyar E. Gasanov, Ivan Pavisic | 2003-04-22 |
| 6550045 | Changing clock delays in an integrated circuit for skew optimization | Ivan Pavisic, Andrej A. Zolotykj, Elyar E. Gasanov | 2003-04-15 |
| 6550044 | Method in integrating clock tree synthesis and timing optimization for an integrated circuit design | Ivan Pavisic, Andrej A. Zolotykh, Elyar E. Gasanov | 2003-04-15 |
| 6546541 | Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances | Dusan Petranovic, Ivan Pavisic | 2003-04-08 |
| 6487697 | Distribution dependent clustering in buffer insertion of high fanout nets | Ivan Pavisic, Andrej A. Zolotykh | 2002-11-26 |
| 6470487 | Parallelization of resynthesis | Andrej A. Zolotykh, Elyar E. Gasanov, Ivan Pavisic | 2002-10-22 |
| 6463572 | IC timing analysis with known false paths | Ivan Pavisic, Pedja Raspopovic | 2002-10-08 |