Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11694016 | Fast topology bus router for interconnect planning | Zhengtao Yu, Balkrishna R. Rashingkar, Douglas Chang, Yiding Han | 2023-07-04 |
| 10318685 | Management of placement constraint regions in an electronic design automation (EDA) system | Mark William Bales, Jeffrey J. Loescher | 2019-06-11 |
| 9552450 | Determining a user-specified location in a graphical user interface of an electronic design automation tool | Karlo Tskitishvili, Luis D. Guilin, Jeffrey J. Loescher | 2017-01-24 |
| 9460258 | Shaping integrated with power network synthesis (PNS) for power grid (PG) alignment | Yan Lin, Aiguo Lu, Balkrishna R. Rashingkar, Russell B. Segal, Peiqing Zou | 2016-10-04 |
| 8893073 | Displaying a congestion indicator for a channel in a circuit design layout | Balkrishna R. Rashingkar, Russell B. Segal, Douglas Chang, Ksenia Roze | 2014-11-18 |
| 8612913 | Automated approach to planning critical signals and busses | — | 2013-12-17 |
| 8181145 | Method and apparatus for generating a floorplan using a reduced netlist | Kester B. Rice | 2012-05-15 |
| 6624659 | Dynamically updating impedance compensation code for input and output drivers | Isaac Abraham, David R. Johnson, Jed Griffin | 2003-09-23 |