| 12073156 |
Propagating physical design information through logical design hierarchy of an electronic circuit |
Amit Jalota, Andrew T. Saunders, Aruna Kanagaraj, Douglas Chang, Eshwari Rajendran +4 more |
2024-08-27 |
| 11694016 |
Fast topology bus router for interconnect planning |
Zhengtao Yu, David L. Peart, Douglas Chang, Yiding Han |
2023-07-04 |
| 10896280 |
Netlist abstraction for circuit design floorplanning |
Leonardos J. van Bokhoven, Peiqing Zou |
2021-01-19 |
| 10372860 |
Netlist abstraction for circuit design floorplanning |
Leonardus J. van Bokhoven, Peiqing Zou |
2019-08-06 |
| 10318692 |
Scalable chip placement |
Douglas Chang |
2019-06-11 |
| 9747403 |
Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designs |
Yi-Min Jiang, Xiang Qui, Yan Lin |
2017-08-29 |
| 9460258 |
Shaping integrated with power network synthesis (PNS) for power grid (PG) alignment |
David L. Peart, Yan Lin, Aiguo Lu, Russell B. Segal, Peiqing Zou |
2016-10-04 |
| 9026974 |
Semiconductor integrated circuit partitioning and timing |
Russell B. Segal, Douglas Chang, Mattias A. Hembruch |
2015-05-05 |
| 8910097 |
Netlist abstraction |
Douglas Chang |
2014-12-09 |
| 8893073 |
Displaying a congestion indicator for a channel in a circuit design layout |
David L. Peart, Russell B. Segal, Douglas Chang, Ksenia Roze |
2014-11-18 |
| 8001514 |
Method and apparatus for computing a detailed routability estimation |
Douglas Chang, Neeraj Kaul |
2011-08-16 |
| 7313776 |
Method and apparatus for routing an integrated circuit |
Neeraj Kaul, Anthony Tseng, Wei-Chih Tseng |
2007-12-25 |