Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754070 | Path-based floorplan analysis | — | 2017-09-05 |
| 9460258 | Shaping integrated with power network synthesis (PNS) for power grid (PG) alignment | David L. Peart, Yan Lin, Aiguo Lu, Balkrishna R. Rashingkar, Peiqing Zou | 2016-10-04 |
| 9390222 | Determining a set of timing paths for creating a circuit abstraction | Peiqing Zou | 2016-07-12 |
| 9189591 | Path-based floorplan analysis | — | 2015-11-17 |
| 9026974 | Semiconductor integrated circuit partitioning and timing | Balkrishna R. Rashingkar, Douglas Chang, Mattias A. Hembruch | 2015-05-05 |
| 8914759 | Abstract creation | Peiqing Zou | 2014-12-16 |
| 8893073 | Displaying a congestion indicator for a channel in a circuit design layout | Balkrishna R. Rashingkar, David L. Peart, Douglas Chang, Ksenia Roze | 2014-11-18 |
| 7114142 | Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design | Paul Rodman | 2006-09-26 |
| 6678644 | Integrated circuit models having associated timing exception information therewith for use with electronic design automation | — | 2004-01-13 |
| 6496972 | Method and system for circuit design top level and block optimization | — | 2002-12-17 |
| 6438731 | Integrated circuit models having associated timing exception information therewith for use in circuit design optimizations | — | 2002-08-20 |
| 6317863 | Method and apparatus for irregular datapath placement in a datapath placement tool | — | 2001-11-13 |
| 6023568 | Extracting accurate and efficient timing models of latch-based designs | — | 2000-02-08 |
| 5953235 | Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof | Brent Gregory | 1999-09-14 |
| 5790830 | Extracting accurate and efficient timing models of latch-based designs | — | 1998-08-04 |
| 5748488 | Method for generating a logic circuit from a hardware independent user description using assignment conditions | Brent Gregory | 1998-05-05 |
| 5737574 | Method for generating a logic circuit from a hardware independent user description using mux conditions and hardware selectors | Brent Gregory | 1998-04-07 |
| 5691911 | Method for pre-processing a hardware independent description of a logic circuit | Brent Gregory | 1997-11-25 |
| 5680318 | Synthesizer for generating a logic network using a hardware independent description | Brent Gregory | 1997-10-21 |
| 5661661 | Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof | Brent Gregory | 1997-08-26 |
| 5581781 | Synthesizer for generating a logic network using a hardware independent description | Brent Gregory | 1996-12-03 |
| 5530841 | Method for converting a hardware independent user description of a logic circuit into hardware components | Brent Gregory | 1996-06-25 |