Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11983297 | Efficient statistical techniques for detecting sensitive data | Aurelian Tutuianu, Daniel Voinea, Petru-Serban Cehan, Silviu Catalin Poede, Adrian Cadar +1 more | 2024-05-14 |
| 11797705 | Generative adversarial network for named entity recognition | Daniel Voinea, Aurelian Tutuianu, Silviu Catalin Poede, Marian-Razvan Udrea | 2023-10-24 |
| 11599667 | Efficient statistical techniques for detecting sensitive data | Aurelian Tutuianu, Daniel Voinea, Petru-Serban Cehan, Silviu Catalin Poede, Adrian Cadar +1 more | 2023-03-07 |
| 10346578 | Placement-based congestion-aware logic restructuring | Jagat Patel, William C. Naylor | 2019-07-09 |
| 10331834 | Optimizing the ordering of the inputs to large commutative-associative trees of logic gates | Bogdan Craciun, Jaime Wong, William C. Naylor | 2019-06-25 |
| 8146047 | Automation method and system for assessing timing based on gaussian slack | William C. Naylor, Bogdan Craciun | 2012-03-27 |
| 7484194 | Automation method and system for assessing timing based on Gaussian slack | William C. Naylor, Bogdan Craciun | 2009-01-27 |
| 6132109 | Architecture and methods for a hardware description language source level debugging system | Trinanjan Chatterjee, Jing C. Lin, Srinivas Raghvendra, Emil Girczyc, Paul II Estrada +1 more | 2000-10-17 |
| 5953235 | Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof | Russell B. Segal | 1999-09-14 |
| 5937190 | Architecture and methods for a hardware description language source level analysis and debugging system | Trinanjan Chatterjee, Jing C. Lin, Srinivas Raghvendra, Emil Girczyc, Paul II Estrada +1 more | 1999-08-10 |
| 5870608 | Method and apparatus for displaying text including context sensitive information derived from parse tree | — | 1999-02-09 |
| 5748488 | Method for generating a logic circuit from a hardware independent user description using assignment conditions | Russell B. Segal | 1998-05-05 |
| 5737574 | Method for generating a logic circuit from a hardware independent user description using mux conditions and hardware selectors | Russell B. Segal | 1998-04-07 |
| 5691911 | Method for pre-processing a hardware independent description of a logic circuit | Russell B. Segal | 1997-11-25 |
| 5680318 | Synthesizer for generating a logic network using a hardware independent description | Russell B. Segal | 1997-10-21 |
| 5661661 | Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof | Russell B. Segal | 1997-08-26 |
| 5581781 | Synthesizer for generating a logic network using a hardware independent description | Russell B. Segal | 1996-12-03 |
| 5530841 | Method for converting a hardware independent user description of a logic circuit into hardware components | Russell B. Segal | 1996-06-25 |