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Paul Rodman — 30 Patents

REReshape: 9 patents #2 of 5Top 40%

PCPrime Computer: 5 patents #3 of 116Top 3%

SGSilicon Graphics: 4 patents #113 of 758Top 15%

MTMips Technologies: 2 patents #69 of 129Top 55%

Google: 2 patents #10,599 of 22,993Top 50%

MAMagma Design Automation: 2 patents #11 of 56Top 20%

DEDigital Equipment: 2 patents #602 of 2,100Top 30%

Kabushiki Kaisha Toshiba: 1 patents #13,641 of 21,451Top 65%

Ashland, MA: #15 of 345 inventorsTop 5%

Massachusetts: #3,129 of 88,656 inventorsTop 4%

Overall (All Time): #121,623 of 4,157,543Top 3%

30 Patents All Time

Paul Rodman has been granted 30 US patents while listed as an inventor at Reshape. The first was granted in 1985 and the most recent in January 2015. Paul Rodman ranks #121,623 of 4,157,543 US inventors in our database (top 2.9%). Patent records list Paul Rodman in Ashland, MA, US.

Patents per Year

Issued Patents All Time

Showing 1–25 of 30 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8930594	Integrated circuit with a pinmux crossbar and virtual pins for peripheral connectivity	Donald C. Stark	2015-01-06	$11,326,000
8130881	MIMO with reduced compute complexity	Carroll Philip Gossett, Michial Allen Gunter	2012-03-06	$55,319,000
7185305	Creating a power distribution arrangement with tapered metal wires for a physical design	—	2007-02-27	$3,851,000
7155693	Floorplanning a hierarchical physical design to improve placement and routing	—	2006-12-26	$1,666,000
7114142	Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design	Russell B. Segal	2006-09-26	$3,363,000
6865721	Optimization of the top level in abutted-pin hierarchical physical design	Peter Dahl, Byron Dickinson, Margie Levine	2005-03-08
6857116	Optimization of abutted-pin hierarchical physical design	Peter Dahl, Byron Dickinson, Margie Levine	2005-02-15
6854093	Facilitating press operation in abutted-pin hierarchical physical design	Peter Dahl, Byron Dickinson, Margie Levine	2005-02-08
6757874	Facilitating verification in abutted-pin hierarchical physical design	Peter Dahl, Byron Dickinson, Margie Levine	2004-06-29
6691221	Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution	Chandra Joshi, Peter Hsu, Monica R. Nofal	2004-02-10	$4,016,000
6574788	Method and system for automatically generating low level program commands as dependency graphs from high level physical design stages	Margie Levine, Peter Dahl, Byron Dickinson, Jagat Patel	2003-06-03
6564363	Method and system for implementing a graphical user interface for defining and linking multiple attach points for multiple blocks of an integrated circuit netlist	Peter Dahl, Byron Dickinson, Margie Levine	2003-05-13
6564364	Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file	Peter Dahl, Byron Dickinson, Margie Levine	2003-05-13
6557153	Method and system for implementing a user interface for performing physical design operations on an integrated circuit netlist	Peter Dahl, Byron Dickinson, Margie Levine	2003-04-29
6553554	Method and system for implementing a graphical user interface for depicting loose fly line interconnections between multiple blocks of an integrated circuit netlist	Peter Dahl, Byron Dickinson, Margie Levine	2003-04-22
6247124	Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions	Chandra Joshi, Peter Hsu, Monica R. Nofal	2001-06-12
5954815	Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address	Chandra Joshi, Peter Hsu, Monica R. Nofal	1999-09-21	$38,018,000
5757658	Procedure and system for placement optimization of cells within circuit blocks by optimizing placement of input/output ports within an integrated circuit design	Marjorie S. Levine	1998-05-26	$17,185,000
5604909	Apparatus for processing instructions in a computing system	Chandra Joshi, Peter Hsu, Monica R. Nofal	1997-02-18
5537538	Debug mode for a superscalar RISC processor	Joseph P. Bratt, John Brennan, Peter Hsu, Chandra Joshi, William A. Huffman +3 more	1996-07-16	$44,287,000
5510934	Memory system including local and global caches for storing floating point and integer data	John Brennan, Peter Hsu, William A. Huffman, Joseph T. Scanlon, Man Kit Tang +1 more	1996-04-23	$52,517,000
5179680	Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus	Robert P. Colwell, John O'Donnell, David B. Papworth	1993-01-12	$5,559,000
5057837	Instruction storage method with a compressed format using a mask word	Robert P. Colwell, John O'Donnell, David B. Papworth	1991-10-15	$9,561,000
4920477	Virtual address table look aside buffer miss recovery method and apparatus	Robert P. Colwell, John O'Donnell, David B. Papworth	1990-04-24
4833599	Hierarchical priority branch handling for parallel execution in a parallel processor	Robert P. Colwell, John O'Donnell, David B. Papworth	1989-05-23