Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6691221 | Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution | Chandra Joshi, Paul Rodman, Peter Hsu | 2004-02-10 |
| 6247124 | Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions | Chandra Joshi, Paul Rodman, Peter Hsu | 2001-06-12 |
| 5954815 | Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address | Chandra Joshi, Paul Rodman, Peter Hsu | 1999-09-21 |
| 5604909 | Apparatus for processing instructions in a computing system | Chandra Joshi, Paul Rodman, Peter Hsu | 1997-02-18 |
| 5537538 | Debug mode for a superscalar RISC processor | Joseph P. Bratt, John Brennan, Peter Hsu, Chandra Joshi, William A. Huffman +3 more | 1996-07-16 |