Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8180998 | System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations | Monier Maher, Christopher Lamb, Sanjay Patel | 2012-05-15 |
| 8074058 | Providing extended precision in SIMD vector arithmetic operations | Timothy J. Van Hook, William A. Huffman, Henry Packard Moreton, Earl A. Killian | 2011-12-06 |
| 7793077 | Alignment and ordering of vector elements for single instruction multiple data processing | Timothy J. Van Hook, William A. Huffman, Henry Packard Moreton, Earl A. Killian | 2010-09-07 |
| 7546443 | Providing extended precision in SIMD vector arithmetic operations | Timothy J. Van Hook, William A. Huffman, Henry Packard Moreton, Earl A. Killian | 2009-06-09 |
| 7197625 | Alignment and ordering of vector elements for single instruction multiple data processing | Timothy J. Van Hook, William A. Huffman, Henry Packard Moreton, Earl A. Killian | 2007-03-27 |
| 7159100 | Method for providing extended precision in SIMD vector arithmetic operations | Timothy J. Van Hook, William A. Huffman, Henry Packard Moreton, Earl A. Killian | 2007-01-02 |
| 6859862 | Method and apparatus for software management of on-chip cache | Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng | 2005-02-22 |
| 6691221 | Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution | Chandra Joshi, Paul Rodman, Monica R. Nofal | 2004-02-10 |
| 6681296 | Method and apparatus for software management of on-chip cache | Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng | 2004-01-20 |
| 6247124 | Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions | Chandra Joshi, Paul Rodman, Monica R. Nofal | 2001-06-12 |
| 5954815 | Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address | Chandra Joshi, Paul Rodman, Monica R. Nofal | 1999-09-21 |
| 5933650 | Alignment and ordering of vector elements for single instruction multiple data processing | Timothy J. Van Hook, William A. Huffman, Henry Packard Moreton, Earl A. Killian | 1999-08-03 |
| 5864703 | Method for providing extended precision in SIMD vector arithmetic operations | Timothy J. Van Hook, William A. Huffman, Henry Packard Moreton, Earl A. Killian | 1999-01-26 |
| 5740402 | Conflict resolution in interleaved memory systems with multiple parallel accesses | Joseph P. Bratt, John F. Brennen, Joseph T. Scanlon, Man Kit Tang, Steven J. Ciavaglia | 1998-04-14 |
| 5632025 | Method for preventing multi-level cache system deadlock in a multi-processor system | Joseph P. Bratt, John Brennan, William A. Huffman, Joseph T. Scanlon, Steve J. Ciavaglia | 1997-05-20 |
| 5604909 | Apparatus for processing instructions in a computing system | Chandra Joshi, Paul Rodman, Monica R. Nofal | 1997-02-18 |
| 5572704 | System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes | Joseph P. Bratt, John Brennan, William A. Huffman, Joseph T. Scanlon, Steve Ciavagia | 1996-11-05 |
| 5537538 | Debug mode for a superscalar RISC processor | Joseph P. Bratt, John Brennan, Chandra Joshi, William A. Huffman, Monica R. Nofal +3 more | 1996-07-16 |
| 5526504 | Variable page size translation lookaside buffer | Joseph T. Scanlon, Steve J. Ciavaglia | 1996-06-11 |
| 5510934 | Memory system including local and global caches for storing floating point and integer data | John Brennan, William A. Huffman, Paul Rodman, Joseph T. Scanlon, Man Kit Tang +1 more | 1996-04-23 |