Issued Patents All Time
Showing 26–50 of 177 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7818703 | Density driven layout for RRAM configuration module | Ivan Pavisic, Anatoli Bolotov | 2010-10-19 |
| 7739575 | Pipelined LDPC arithmetic unit | Vojislav Vukovic, Ranko Scepanovic | 2010-06-15 |
| 7739471 | High performance tiling for RRAM memory | Igor Vikhliantsev, Ranko Scepanovic | 2010-06-15 |
| 7667494 | Methods and apparatus for fast unbalanced pipeline architecture | Ivan Pavisic, Igor Vikhliantsev | 2010-02-23 |
| 7656325 | Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data | — | 2010-02-02 |
| 7548844 | Sequential tester for longest prefix search engines | Anatoli Bolotov | 2009-06-16 |
| 7546505 | Built in self test transport controller architecture | Sergey Gribok, Ivan Pavisic | 2009-06-09 |
| 7512918 | Multimode delay analysis for simplifying integrated circuit design timing models | Andrey Nikitin, Ranko Scepanovic | 2009-03-31 |
| 7493519 | RRAM memory error emulation | Vojislav Vukovic, Sergey Gribok | 2009-02-17 |
| 7472358 | Method and system for outputting a sequence of commands and data described by a flowchart | Andrey Nikitin, Ranko Scepanovic | 2008-12-30 |
| 7430694 | Memory BISR architecture for a slice | Sergey Gribok, Anatoli Bolotov | 2008-09-30 |
| 7415691 | Method and system for outputting a sequence of commands and data described by a flowchart | Andrey Nikitin, Ranko Scepanovic | 2008-08-19 |
| 7415686 | Memory timing model with back-annotating | Anatoli Bolotov, Ranko Scepanovic | 2008-08-19 |
| 7404166 | Method and system for mapping netlist of integrated circuit to design | Pavel A. Panteleev, Andrey Nikitin | 2008-07-22 |
| 7380223 | Method and system for converting netlist of integrated circuit between libraries | Pavel A. Panteleev, Andrey Nikitin | 2008-05-27 |
| 7356743 | RRAM controller built in self test memory | Andrey Nikitin, Ilya V. Neznanov | 2008-04-08 |
| 7328382 | Memory BISR controller architecture | Sergey Gribok, Anatoli Bolotov | 2008-02-05 |
| 7328423 | Method for evaluating logic functions by logic circuits having optimized number of and/or switches | Andrey Nikitin | 2008-02-05 |
| 7315993 | Verification of RRAM tiling netlist | Andrey Nikitin, Ranko Scepanovic | 2008-01-01 |
| 7313660 | Data stream frequency reduction and/or phase shift | Igor Vikhliantsev, Vojislav Vukovic | 2007-12-25 |
| 7305593 | Memory mapping for parallel turbo decoding | Anatoli Bolotov, Ranko Scepanovic | 2007-12-04 |
| 7305597 | System and method for efficiently testing a large random access memory space | Ranko Scepanovic | 2007-12-04 |
| 7283385 | RRAM communication system | Sergey Gribok, Anatoli Bolotov | 2007-10-16 |
| 7263470 | Digital gaussian noise simulator | Andrey Nikitin, Igor Vikhliantsev | 2007-08-28 |
| 7257807 | Method for optimizing execution time of parallel processor programs | Andrey Nikitin | 2007-08-14 |