Issued Patents All Time
Showing 51–75 of 177 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7246337 | Density driven layout for RRAM configuration module | Ivan Pavisic, Anatoli Bolotov | 2007-07-17 |
| 7231383 | Search engine for large-width data | Anatoli Bolotov, Ranko Scepanovic | 2007-06-12 |
| 7219321 | Process and apparatus for memory mapping | Andrey Nikitin, Anatoli Bolotov | 2007-05-15 |
| 7216278 | Method and BIST architecture for fast memory testing in platform-based integrated circuit | Anatoli Bolotov, Ranko Scepanovic | 2007-05-08 |
| 7210113 | Process and apparatus for placing cells in an IC floorplan | Andrey Nikitin, Igor Vikhliantsev | 2007-04-24 |
| 7200785 | Sequential tester for longest prefix search engines | Anatoli Bolotov | 2007-04-03 |
| 7193905 | RRAM flipflop rcell memory generator | Sergei B. Gashkov, Oleg B. Sedelev, Andrey Nikitin | 2007-03-20 |
| 7194717 | Compact custom layout for RRAM column controller | Ivan Pavisic, Anatoli Bolotov | 2007-03-20 |
| 7181563 | FIFO memory with single port memory modules for allowing simultaneous read and write operations | Anatoli Bolotov, Ranko Scepanovic | 2007-02-20 |
| 7167886 | Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2 | Sergei B. Gashkov | 2007-01-23 |
| 7168052 | Yield driven memory placement system | Andrey Nikitin, Ranko Scepanovic | 2007-01-23 |
| 7111264 | Process and apparatus for fast assignment of objects to a rectangle | Andrey Nikitin, Ranko Scepanovic | 2006-09-19 |
| 7103868 | Optimizing depths of circuits for Boolean functions | Andrey Nikitin | 2006-09-05 |
| 7096413 | Decomposer for parallel turbo decoding, process and integrated circuit | Ranko Scepanovic, Vojislav Vukovic | 2006-08-22 |
| 7082593 | Method and apparatus of IC implementation based on C++ language description | Andrey Nikitin | 2006-07-25 |
| 7082561 | Built-in functional tester for search engines | Anatoli Bolotov, Nikola Radovanovic | 2006-07-25 |
| 7072922 | Integrated circuit and process for identifying minimum or maximum input value among plural inputs | Anatoli Bolotov, Igor Vikhliantsev | 2006-07-04 |
| 7065606 | Controller architecture for memory mapping | Igor Vikhliantsev, Ranko Scepanovic | 2006-06-20 |
| 7062726 | Method for generating tech-library for logic function | Igor Vikhliantsev, Anatoli Bolotov | 2006-06-13 |
| 7050582 | Pseudo-random one-to-one circuit synthesis | Igor Vikhliantsev, Ranko Scepanovic | 2006-05-23 |
| 7039855 | Decision function generator for a Viterbi decoder | Andrey Nikitin | 2006-05-02 |
| 7036102 | Process and apparatus for placement of cells in an IC during floorplan creation | Andrey Nikitin, Igor Vikhliantsev | 2006-04-25 |
| 7035844 | FFS search and edit pipeline separation | Ranko Scepanovic | 2006-04-25 |
| 7028274 | RRAM backend flow | Ranko Scepanovic, Ivan Pavisic, Vojislav Vukovic | 2006-04-11 |
| 7003510 | Table module compiler equivalent to ROM | Ranko Scepanovic | 2006-02-21 |