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Feedback programmable data strobe enable architecture for DDR memory applications |
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Method and computer program for generating grounded shielding wires for signal wiring |
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Memory interface architecture for maximizing access timing margin |
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Signal delay skew reduction system |
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System for glitch-free delay updates of a standard cell-based programmable delay |
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Low-power, programmable multi-stage delay cell |
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DQS strobe centering (data eye training) method |
Derrick Sai-Tang Butt |
2008-10-28 |
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Programmable data strobe enable architecture for DDR memory applications |
Derrick Sai-Tang Butt |
2008-07-01 |
| 7215584 |
Method and/or apparatus for training DQS strobe gating |
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2007-05-08 |
