TM

Terence J. Magee

AM AMD: 9 patents #1,329 of 9,279Top 15%
LS Lsi: 6 patents #222 of 1,740Top 15%
Lsi Logic: 1 patents #1,146 of 1,957Top 60%
IN Intel: 1 patents #18,218 of 30,777Top 60%
Overall (All Time): #270,784 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11789641 Three dimensional circuit systems and methods having memory hierarchies Scott J. Weber, Jawad B. Khan, Ilya K. Ganusov, Martin Langhammer, Matthew J. Adiletta +5 more 2023-10-17
10103718 Recalibration of source synchronous systems Richard W. Swanson, Qi Zhang, Srinivas Vura 2018-10-16
10009197 Method and apparatus for intersymbol interference compensation Asim A. Patel 2018-06-26
9557766 High-speed serial data interface for a physical layer interface Nicholas J. Sawyer 2017-01-31
9355696 Calibration in a control device receiving from a source synchronous interface Xiaoqian Zhang 2016-05-31
9330749 Dynamic selection of output delay in a memory control device Dhruv Choksey 2016-05-03
9331701 Receivers and methods of enabling the calibration of circuits receiving input data Xiaoqian Zhang 2016-05-03
9324409 Method and apparatus for gating a strobe signal from a memory and subsequent tracking of the strobe signal over time Jayant Mittal 2016-04-26
9281049 Read clock forwarding for multiple source-synchronous memory interfaces Jayant Mittal 2016-03-08
9224444 Method and apparatus for VT invariant SDRAM write leveling and fast rank switching Sathappan Ravi, Dhruv Choksey 2015-12-29
8743634 Generic low power strobe based system and method for interfacing memory controller and source synchronous memory Cheng-Gang Kong 2014-06-03
8453096 Non-linear common coarse delay system and method for delaying data strobe Christopher Paulson, Cheng-Gang Kong 2013-05-28
7969799 Multiple memory standard physical layer macro function Derrick Sai-Tang Butt, Cheng-Gang Kong, Thomas Hughes 2011-06-28
7865661 Configurable high-speed memory interface subsystem Derrick Sai-Tang Butt, Cheng-Gang Kong 2011-01-04
7605628 System for glitch-free delay updates of a standard cell-based programmable delay Thomas Hughes, Hui-Yin Seto 2009-10-20
7454303 System and method for compensating for PVT variation effects on the delay line of a clock signal Thomas Hughes, Cheng-Gang Kong 2008-11-18
7437500 Configurable high-speed memory interface subsystem Derrick Sai-Tang Butt, Cheng-Gang Kong 2008-10-14