Terence J. Magee — 17 Patents at AMD

Terence J. Magee has been granted 17 US patents while listed as an inventor at AMD. The first was granted in 2008 and the most recent in October 2023. Terence J. Magee ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Terence J. Magee in San Francisco, CA, US.

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11789641	Three dimensional circuit systems and methods having memory hierarchies	Scott J. Weber, Jawad B. Khan, Ilya K. Ganusov, Martin Langhammer, Matthew J. Adiletta +5 more	2023-10-17	$15,641,000
10103718	Recalibration of source synchronous systems	Richard W. Swanson, Qi Zhang, Srinivas Vura	2018-10-16	$35,291,000
10009197	Method and apparatus for intersymbol interference compensation	Asim A. Patel	2018-06-26	$82,781,000
9557766	High-speed serial data interface for a physical layer interface	Nicholas J. Sawyer	2017-01-31	$8,527,000
9355696	Calibration in a control device receiving from a source synchronous interface	Xiaoqian Zhang	2016-05-31	$11,154,000
9330749	Dynamic selection of output delay in a memory control device	Dhruv Choksey	2016-05-03	$10,485,000
9331701	Receivers and methods of enabling the calibration of circuits receiving input data	Xiaoqian Zhang	2016-05-03	$10,485,000
9324409	Method and apparatus for gating a strobe signal from a memory and subsequent tracking of the strobe signal over time	Jayant Mittal	2016-04-26	$8,542,000
9281049	Read clock forwarding for multiple source-synchronous memory interfaces	Jayant Mittal	2016-03-08	$27,165,000
9224444	Method and apparatus for VT invariant SDRAM write leveling and fast rank switching	Sathappan Ravi, Dhruv Choksey	2015-12-29	$7,580,000
8743634	Generic low power strobe based system and method for interfacing memory controller and source synchronous memory	Cheng-Gang Kong	2014-06-03
8453096	Non-linear common coarse delay system and method for delaying data strobe	Christopher Paulson, Cheng-Gang Kong	2013-05-28
7969799	Multiple memory standard physical layer macro function	Derrick Sai-Tang Butt, Cheng-Gang Kong, Thomas Hughes	2011-06-28
7865661	Configurable high-speed memory interface subsystem	Derrick Sai-Tang Butt, Cheng-Gang Kong	2011-01-04
7605628	System for glitch-free delay updates of a standard cell-based programmable delay	Thomas Hughes, Hui-Yin Seto	2009-10-20	$14,074,000
7454303	System and method for compensating for PVT variation effects on the delay line of a clock signal	Thomas Hughes, Cheng-Gang Kong	2008-11-18	$5,408,000
7437500	Configurable high-speed memory interface subsystem	Derrick Sai-Tang Butt, Cheng-Gang Kong	2008-10-14	$11,302,000

Terence J. Magee — 17 Patents

Issued Patents All Time

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