IY

Irwin Yablok

IN Intel: 10 patents #4,046 of 30,777Top 15%
SA Siltronic Ag: 1 patents #145 of 300Top 50%
Overall (All Time): #511,146 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9691632 Epitaxial wafer and a method of manufacturing thereof Peter Storck, Norbert Werner, Martin Vorderwestner, Peter G. Tolchinsky 2017-06-27
7531429 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices Peter G. Tolchinsky, Chuan Hu, Richard Emery 2009-05-12
7491988 Transistors with increased mobility in the channel zone and method of fabrication Peter G. Tolchinsky, Mark Bohr 2009-02-17
7473614 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Mohamad A. Shaheen 2009-01-06
7378331 Methods of vertically stacking wafers using porous silicon Mohamad A. Shaheen, Peter G. Tolchinsky, Scott R. List 2008-05-27
7161224 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process Peter G. Tolchinsky, Mohamad A. Shaheen, Ryan Lei 2007-01-09
7091108 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices Peter G. Tolchinsky, Chuan Hu, Richard Emery 2006-08-15
6924543 Method for making a semiconductor device having increased carrier mobility Peter G. Tolchinsky 2005-08-02
6911380 Method of forming silicon on insulator wafers Peter G. Tolchinsky, Mohamad A. Shaheen 2005-06-28
6908027 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process Peter G. Tolchinsky, Mohamad A. Shaheen, Ryan Lei 2005-06-21