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USPTO Patent Rankings Data through Dec 31, 2025
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Irwin Yablok — 10 Patents

Intel: 10 patents #4,072 of 30,777Top 15%
SASiltronic Ag: 1 patents #145 of 300Top 50%
Portland, OR: #1,745 of 9,213 inventorsTop 20%
Oregon: #4,318 of 28,073 inventorsTop 20%
Overall (All Time): #481,000 of 4,157,543Top 15%
10 Patents All Time
Irwin Yablok has been granted 10 US patents while listed as an inventor at Intel. The first was granted in 2005 and the most recent in June 2017. Irwin Yablok ranks #481,000 of 4,157,543 US inventors in our database (top 11.6%). Patent records list Irwin Yablok in Portland, OR, US.

Issued Patents All Time

Showing 1–10 of 10 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9691632 Epitaxial wafer and a method of manufacturing thereof Peter Storck, Norbert Werner, Martin Vorderwestner, Peter G. Tolchinsky 2017-06-27
7531429 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices Peter G. Tolchinsky, Chuan Hu, Richard Emery 2009-05-12 $14,965,000
7491988 Transistors with increased mobility in the channel zone and method of fabrication Peter G. Tolchinsky, Mark Bohr 2009-02-17 $14,413,000
7473614 Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Mohamad A. Shaheen 2009-01-06 $21,219,000
7378331 Methods of vertically stacking wafers using porous silicon Mohamad A. Shaheen, Peter G. Tolchinsky, Scott R. List 2008-05-27 $24,811,000
7161224 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process Peter G. Tolchinsky, Mohamad A. Shaheen, Ryan Lei 2007-01-09 $12,865,000
7091108 Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices Peter G. Tolchinsky, Chuan Hu, Richard Emery 2006-08-15 $13,533,000
6924543 Method for making a semiconductor device having increased carrier mobility Peter G. Tolchinsky 2005-08-02 $20,766,000
6911380 Method of forming silicon on insulator wafers Peter G. Tolchinsky, Mohamad A. Shaheen 2005-06-28 $36,074,000
6908027 Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process Peter G. Tolchinsky, Mohamad A. Shaheen, Ryan Lei 2005-06-21 $21,477,000