Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JK

Jun Sung Kang — 16 Patents

Intel: 16 patents #2,596 of 30,777Top 9%
Portland, OR: #1,150 of 9,213 inventorsTop 15%
Oregon: #2,717 of 28,073 inventorsTop 10%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Jun Sung Kang has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 2019 and the most recent in July 2025. Jun Sung Kang ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Jun Sung Kang in Portland, OR, US.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12349394 Dielectric isolation layer between a nanowire transistor and a substrate Bruce Beattie, Leonard P. GULER, Biswajeet Guha, William Hsu 2025-07-01
12328905 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Bruce Beattie +1 more 2025-06-10
12302632 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu, Dax M. Crum +2 more 2025-05-13
11929396 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Bruce Beattie +1 more 2024-03-12 $37,196,000
11901458 Dielectric isolation layer between a nanowire transistor and a substrate Bruce Beattie, Leonard P. GULER, Biswajeet Guha, William Hsu 2024-02-13 $18,546,000
11869973 Nanowire transistor structure and method of shaping Erica J. Thompson, Aditya Kasukurti, Kai Loon Cheong, Biswajeet Guha, William Hsu +1 more 2024-01-09 $30,329,000
11869891 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu, Dax M. Crum +2 more 2024-01-09 $30,329,000
11715787 Self-aligned nanowire Mark Armstrong, Biswajeet Guha, Bruce Beattie, Tahir Ghani 2023-08-01 $26,467,000
11404578 Dielectric isolation layer between a nanowire transistor and a substrate Bruce Beattie, Leonard P. GULER, Biswajeet Guha, William Hsu 2022-08-02 $13,520,000
11342411 Cavity spacer for nanowire transistors William Hsu, Biswajeet Guha, Leonard P. GULER, Souvik Chakrabarty, Bruce Beattie +1 more 2022-05-24 $18,289,000
11276691 Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths Biswajeet Guha, Bruce Beattie, Stephen M. Cea, Tahir Ghani 2022-03-15 $18,336,000
11205715 Self-aligned nanowire Mark Armstrong, Biswajeet Guha, Bruce Beattie, Tahir Ghani 2021-12-21 $33,282,000
11069795 Transistors with channel and sub-channel regions with distinct compositions and dimensions Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Bruce Beattie, Anupama Bowonder +3 more 2021-07-20 $44,320,000
10944006 Geometry tuning of fin based transistor Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Chandra S. Mohapatra, Hei Kam +2 more 2021-03-09 $45,039,000
10672868 Methods of forming self aligned spacers for nanowire device structures Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Seiyon Kim 2020-06-02 $32,838,000
10516021 Reduced leakage transistors with germanium-rich channel regions Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Seiyon Kim 2019-12-24 $26,956,000