Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11769836 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Susmita Ghose, Zachary Geiger | 2023-09-26 |
| 11757037 | Epitaxial oxide plug for strained transistors | Karthik Jambunathan, Anupama Bowonder, Anand S. Murthy, Tahir Ghani | 2023-09-12 |
| 11749733 | FIN shaping using templates and integrated circuit structures resulting therefrom | Leonard P. GULER, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar | 2023-09-05 |
| 11742410 | Gate-all-around integrated circuit structures having oxide sub-fins | Leonard P. GULER, Tahir Ghani, Swaminathan Sivakumar | 2023-08-29 |
| 11715787 | Self-aligned nanowire | Mark Armstrong, Jun Sung Kang, Bruce Beattie, Tahir Ghani | 2023-08-01 |
| 11715775 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Leonard P. GULER, Tahir Ghani, Swaminathan Sivakumar | 2023-08-01 |
| 11705518 | Isolation schemes for gate-all-around transistor devices | Rishabh Mehandru, Stephen M. Cea, Tahir Ghani, William Hsu | 2023-07-18 |
| 11676965 | Strained tunable nanowire structures and process | Stephen M. Cea, Tahir Ghani, Anand S. Murthy | 2023-06-13 |
| 11621354 | Integrated circuit structures having partitioned source or drain contact structures | Mauro J. Kobrinsky, Stephanie A. Bojarski, Babita Dhayal, Tahir Ghani | 2023-04-04 |
| 11594637 | Gate-all-around integrated circuit structures having fin stack isolation | Leonard P. GULER, Stephen D. Snyder, William Hsu, Urusa Alaan, Tahir Ghani +4 more | 2023-02-28 |
| 11588052 | Sub-Fin isolation schemes for gate-all-around transistor devices | William Hsu, Tahir Ghani | 2023-02-21 |
| 11581315 | Self-aligned gate edge trigate and finFET devices | Szuya S. Liao, Tahir Ghani, Christopher KENYON, Leonard P. GULER | 2023-02-14 |
| 11569370 | DEPOP using cyclic selective spacer etch | Leonard P. GULER, Vivek Thirtha, Shu Zhou, Nitesh Kumar, William Hsu +4 more | 2023-01-31 |
| 11538937 | Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material | Leonard P. GULER, Nick Lindert, Swaminathan Sivakumar, Tahir Ghani | 2022-12-27 |
| 11538806 | Gate-all-around integrated circuit structures having high mobility | Roza Kotlyar, Rishabh Mehandru, Stephen M. Cea, Dax M. Crum, Tahir Ghani | 2022-12-27 |
| 11527640 | Wrap-around contact structures for semiconductor nanowires and nanoribbons | Rishabh Mehandru, Tahir Ghani, Stephen M. Cea | 2022-12-13 |
| 11527612 | Gate-all-around integrated circuit structures having vertically discrete source or drain structures | Glenn A. Glass, Anand S. Murthy, Dax M. Crum, Sean T. Ma, Tahir Ghani +3 more | 2022-12-13 |
| 11521968 | Channel structures with sub-fin dopant diffusion blocking layers | Cory Bomberger, Anand S. Murthy, Stephen M. Cea, Anupama Bowonder, Tahir Ghani | 2022-12-06 |
| 11522048 | Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs | Cory Bomberger, Anand S. Murthy, Mark Bohr, Tahir Ghani | 2022-12-06 |
| 11495672 | Increased transistor source/drain contact area using sacrificial source/drain layer | Dax M. Crum, William Hsu, Stephen M. Cea, Tahir Ghani | 2022-11-08 |
| 11469299 | Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers | Glenn A. Glass, Anand S. Murthy, Dax M. Crum, Patrick H. Keys, Tahir Ghani +2 more | 2022-10-11 |
| 11456357 | Self-aligned gate edge architecture with alternate channel material | Anupama Bowonder, William Hsu, Szuya S. Liao, Mehmet O. Baykan, Tahir Ghani | 2022-09-27 |
| 11450738 | Source/drain regions in integrated circuit structures | Sean T. Ma, Anand S. Murthy, Glenn A. Glass | 2022-09-20 |
| 11450739 | Germanium-rich nanowire transistor with relaxed buffer layer | Glenn A. Glass, Anand S. Murthy, Cory Bomberger, Tahir Ghani, Jack T. Kavalieros +3 more | 2022-09-20 |
| 11430868 | Buried etch-stop layer to help control transistor source/drain depth | Rishabh Mehandru, Anupama Bowonder, Anand S. Murthy, Tahir Ghani, Stephen M. Cea | 2022-08-30 |