Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11417781 | Gate-all-around integrated circuit structures including varactors | Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan C. Kolluru, Chung-Hsun Lin +2 more | 2022-08-16 |
| 11411096 | Source electrode and drain electrode protection for nanowire transistors | Karthik Jambunathan, Anand S. Murthy, Tahir Ghani | 2022-08-09 |
| 11404578 | Dielectric isolation layer between a nanowire transistor and a substrate | Bruce Beattie, Leonard P. GULER, Jun Sung Kang, William Hsu | 2022-08-02 |
| 11398474 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Tahir Ghani, Swaminathan Sivakumar | 2022-07-26 |
| 11374100 | Source or drain structures with contact etch stop layer | Cory Bomberger, Rishabh Mehandru, Anupama Bowonder, Anand S. Murthy, Tahir Ghani | 2022-06-28 |
| 11367796 | Gate-all-around integrated circuit structures having asymmetric source and drain contact structures | Mauro J. Kobrinsky, Tahir Ghani | 2022-06-21 |
| 11355608 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Leonard P. GULER, Tahir Ghani, Swaminathan Sivakumar | 2022-06-07 |
| 11342411 | Cavity spacer for nanowire transistors | William Hsu, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more | 2022-05-24 |
| 11335807 | Isolation schemes for gate-all-around transistor devices | Rishabh Mehandru, Stephen M. Cea, Tahir Ghani, William Hsu | 2022-05-17 |
| 11302790 | Fin shaping using templates and integrated circuit structures resulting therefrom | Leonard P. GULER, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar | 2022-04-12 |
| 11276691 | Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths | Jun Sung Kang, Bruce Beattie, Stephen M. Cea, Tahir Ghani | 2022-03-15 |
| 11251302 | Epitaxial oxide plug for strained transistors | Karthik Jambunathan, Anupama Bowonder, Anand S. Murthy, Tahir Ghani | 2022-02-15 |
| 11233152 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | William Hsu, Leonard P. GULER, Dax M. Crum, Tahir Ghani | 2022-01-25 |
| 11205715 | Self-aligned nanowire | Mark Armstrong, Jun Sung Kang, Bruce Beattie, Tahir Ghani | 2021-12-21 |
| 11164790 | Integrated nanowire and nanoribbon patterning in transistor manufacture | Leonard P. GULER, Mark Armstrong, Tahir Ghani, William Hsu | 2021-11-02 |
| 11152461 | Semiconductor layer between source/drain regions and gate spacers | Rishabh Mehandru, Anupama Bowonder, Tahir Ghani, Stephen M. Cea, William Hsu +2 more | 2021-10-19 |
| 11069795 | Transistors with channel and sub-channel regions with distinct compositions and dimensions | Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jun Sung Kang, Bruce Beattie +3 more | 2021-07-20 |
| 11043492 | Self-aligned gate edge trigate and finFET devices | Szuya S. Liao, Tahir Ghani, Christopher KENYON, Leonard P. GULER | 2021-06-22 |
| 10944006 | Geometry tuning of fin based transistor | Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Chandra S. Mohapatra, Hei Kam +2 more | 2021-03-09 |
| 10295739 | Athermal optical devices based on composite structures | Michal Lipson | 2019-05-21 |
| 9746612 | Fiber-waveguide evanescent coupler | Michal Lipson | 2017-08-29 |
| 8457453 | Passively-thermally-stabilized photonic apparatus, method, and applications | Michal Lipson | 2013-06-04 |