PN

Paul A. Nyhus

IN Intel: 54 patents #568 of 30,777Top 2%
📍 Portland, OR: #303 of 9,213 inventorsTop 4%
🗺 Oregon: #603 of 28,073 inventorsTop 3%
Overall (All Time): #46,637 of 4,157,543Top 2%
54
Patents All Time

Issued Patents All Time

Showing 26–50 of 54 patents

Patent #TitleCo-InventorsDate
10600678 Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects Charles H. Wallace, Elliot N. Tan, Swaminathan Sivakumar 2020-03-24
10559529 Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefrom Charles H. Wallace, Leonard P. GULER, Manish Chandhok 2020-02-11
10459338 Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging Eungnak Han, Swaminathan Sivakumar, Ernisse Putna 2019-10-29
10338474 Underlying absorbing or conducting layer for Ebeam direct write (EBDW) lithography Shakul Tandon, Yan Borodovsky, Charles H. Wallace 2019-07-02
10325814 Patterning of vertical nanowire transistor channel and gate with directed self assembly Swaminathan Sivakumar 2019-06-18
10319625 Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures Mohit K. HARAN, Charles H. Wallace, Robert M. Bigwood, Deepak S. Rao, Alexander F. Kaplan 2019-06-11
10297467 Self-aligned via and plug patterning for back end of line (BEOL) interconnects Charles H. Wallace 2019-05-21
10211088 Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects Charles H. Wallace, Elliot N. Tan, Swaminathan Sivakumar 2019-02-19
10204830 Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects Charles H. Wallace, Elliot N. Tan, Swaminathan Sivakumar 2019-02-12
9793159 Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects Charles H. Wallace, Elliot N. Tan, Swaminathan Sivakumar 2017-10-17
9793163 Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects Robert L. Bristol, Florian Gstrein, Richard E. Schenker, Charles H. Wallace, Hui Jae Yoo 2017-10-17
9666451 Self-aligned via and plug patterning for back end of line (BEOL) interconnects Charles H. Wallace 2017-05-30
9653576 Patterning of vertical nanowire transistor channel and gate with directed self assembly Swaminathan Sivakumar 2017-05-16
9625815 Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging Eungnak Han, Swaminathan Sivakumar, Ernisse Putna 2017-04-18
9530688 Directed self assembly of block copolymers to form vias aligned with interconnects Swaminathan Sivakumar, Robert L. Bristol 2016-12-27
9431518 Patterning of vertical nanowire transistor channel and gate with directed self assembly Swaminathan Sivakumar 2016-08-30
9285682 Pre-patterned hard mask for ultrafast lithographic imaging Robert L. Bristol, Charles H. Wallace 2016-03-15
9269630 Patterning of vertical nanowire transistor channel and gate with directed self assembly Swaminathan Sivakumar 2016-02-23
9153477 Directed self assembly of block copolymers to form vias aligned with interconnects Swaninathan Sivakumar, Robert L. Bristol 2015-10-06
9054215 Patterning of vertical nanowire transistor channel and gate with directed self assembly Swaminathan Sivakumar 2015-06-09
9005875 Pre-patterned hard mask for ultrafast lithographic imaging Robert L. Bristol, Charles H. Wallace 2015-04-14
8959465 Techniques for phase tuning for process optimization Shem Ogadhoh, Swaminathan Sivakumar, Seongtae Jeong 2015-02-17
7820550 Negative tone double patterning method Charles H. Wallace, Swaminathan Sivakumar 2010-10-26
7816061 Lithography masks for improved line-end patterning Richard E. Schenker, Swaminathan Sivakumar, Sven Henrichs 2010-10-19
7759028 Sub-resolution assist features Charles H. Wallace, Swaminathan Sivakumar 2010-07-20