Issued Patents All Time
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10204830 | Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects | Charles H. Wallace, Paul A. Nyhus, Swaminathan Sivakumar | 2019-02-12 |
| 9793159 | Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects | Charles H. Wallace, Paul A. Nyhus, Swaminathan Sivakumar | 2017-10-17 |
| 9659860 | Method and structure to contact tight pitch conductive layers with guided vias | Richard E. Schenker | 2017-05-23 |
| 9558947 | Pattern decomposition lithography techniques | Charles H. Wallace, Hossam M. Abdallah, Swaminathan Sivakumar, Oleg Golonzka, Robert M. Bigwood | 2017-01-31 |
| 9379010 | Methods for forming interconnect layers having tight pitch interconnect structures | Christopher J. Jezewski, Jasmeet S. Chawla, Kanwal Jit Singh, Alan M. Myers, Richard E. Schenker | 2016-06-28 |
| 8860184 | Spacer assisted pitch division lithography | Swaminathan Sivakumar | 2014-10-14 |
| 8314034 | Feature size reduction | Michael K. Harper | 2012-11-20 |
| 7977248 | Double patterning with single hard mask | Michael K. Harper, James Jeong | 2011-07-12 |