Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Curtis Tsai — 28 Patents

Intel: 27 patents #1,442 of 30,777Top 5%
ADAnalog Devices: 1 patents #1,680 of 1,990Top 85%
Beaverton, OR: #206 of 3,140 inventorsTop 7%
Oregon: #1,435 of 28,073 inventorsTop 6%
Overall (All Time): #134,628 of 4,157,543Top 4%
28 Patents All Time
Curtis Tsai has been granted 28 US patents while listed as an inventor at Intel. The first was granted in 1999 and the most recent in November 2025. Curtis Tsai ranks #134,628 of 4,157,543 US inventors in our database (top 3.2%). Patent records list Curtis Tsai in Beaverton, OR, US.

Patents per Year

Patents granted per year, 1999 to 2025Bar chart with a peak of 5 patents in 2017.peak 51999: 1 patents19992014: 3 patents2015: 2 patents20152016: 1 patents2017: 5 patents20172018: 2 patents2019: 3 patents20192020: 3 patents2022: 1 patents20222023: 2 patents2024: 3 patents20242025: 2 patents2025

Issued Patents All Time

Showing 1–25 of 28 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12471354 Dipole threshold voltage tuning for high voltage transistor stacks Robin Hsin Kuo Chao, Biswajeet Guha, Brian J. Greene, Chien-Ju Lin, Orb Acton 2025-11-11
12317590 Substrate-free integrated circuit structures Biswajeet Guha, Brian J. Greene, Avyaya Jayanthinarasimham, Ayan Kar, Benjamin Orr +9 more 2025-05-27
12166031 Substrate-less electrostatic discharge (ESD) integrated circuit structures Biswajeet Guha, Brian J. Greene, Daniel Schulman, William Hsu, Chung-Hsun Lin +1 more 2024-12-10 $13,394,000
12136628 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2024-11-05 $48,202,000
11881486 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2024-01-23 $52,361,000
11695008 Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez 2023-07-04
11610917 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2023-03-21 $20,076,000
11251201 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2022-02-15 $14,138,000
10847544 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2020-11-24 $25,522,000
10692888 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2020-06-23 $27,746,000
10658361 Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez 2020-05-19 $31,576,000
10505034 Vertical transistor using a through silicon via gate Xiaodong Yang, Jui-Yen Lin, Kinyip Phoa, Nidhi Nidhi, Yi-Wei Chen +2 more 2019-12-10 $22,400,000
10263112 Vertical non-planar semiconductor device for system-on-chip (SoC) applications Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park 2019-04-16 $24,207,000
10229866 On-chip through-body-via capacitors and techniques for forming same Yi-Wei Chen, Kinyip Phoa, Nidhi Nidhi, Jui-Yen Lin, Kun-Huan Shih +2 more 2019-03-12 $21,255,000
10096599 Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez 2018-10-09 $20,353,000
9972642 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2018-05-15 $21,346,000
9806095 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2017-10-31 $13,240,000
9786783 Transistor architecture having extended recessed spacer and source/drain regions and method of making same Walid M. Hafez, Joodong Park, Jeng-Ya David Yeh, Chia-Hong Jan 2017-10-10 $9,084,000
9748252 Antifuse element utilizing non-planar topology Walid M. Hafez, Chia-Hong Jan, Joodong Park, Jeng-Ya David Yeh 2017-08-29 $8,286,000
9741721 Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM) Joodong Park, Gopinath Bhimarasetti, Rahul Ramaswamy, Chia-Hong Jan, Walid M. Hafez +1 more 2017-08-22 $8,061,000
9570467 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2017-02-14 $9,787,000
9520494 Vertical non-planar semiconductor device for system-on-chip (SoC) applications Chia-Hong Jan, Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park 2016-12-13 $15,488,000
9159734 Antifuse element utilizing non-planar topology Walid M. Hafez, Chia-Hong Jan, Joodong Park, Jeng-Ya David Yeh 2015-10-13 $14,687,000
8981481 High voltage three-dimensional devices having dielectric liners Walid M. Hafez, Jeng-Ya David Yeh, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2015-03-17 $11,864,000
8889508 Precision resistor for non-planar semiconductor device architecture Jeng-Ya David Yeh, Peter J. Vandervoorn, Walid M. Hafez, Chia-Hong Jan, Joodong Park 2014-11-18 $17,555,000