Issued Patents All Time
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12046680 | Inner spacer formation for nanosheet transistors | Yi Song, Chi-Chun Liu, Muthumanickam Sankarapandian | 2024-07-23 |
| 11990530 | Replacement-channel fabrication of III-V nanosheet devices | Jingyun Zhang, Choonghyun Lee, Chun Wing Yeung, Heng Wu | 2024-05-21 |
| 11842998 | Semiconductor device and method of forming the semiconductor device | Hemanth Jagannathan, Choonghyun Lee, Chun Wing Yeung, Jingyun Zhang | 2023-12-12 |
| 11742409 | Replacement-channel fabrication of III-V nanosheet devices | Jingyun Zhang, Choonghyun Lee, Chun Wing Yeung, Heng Wu | 2023-08-29 |
| 11568101 | Predictive multi-stage modelling for complex process control | Scott D. Halle, Kyong Min Yeo, Derren N. Dunn | 2023-01-31 |
| 11199505 | Machine learning enhanced optical-based screening for in-line wafer testing | Mary Breton, Huai Huang, Dexin Kong, Lawrence A. Clevenger | 2021-12-14 |
| 11081567 | Replacement-channel fabrication of III-V nanosheet devices | Jingyun Zhang, Choonghyun Lee, Chun Wing Yeung, Heng Wu | 2021-08-03 |
| 11079337 | Secure wafer inspection and identification | Fee Li Lie, Effendi Leobandung, Richard C. Johnson, Scott D. Halle | 2021-08-03 |
| 10985273 | Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile | Chun Wing Yeung, Choonghyun Lee, Jingyun Zhang, Heng Wu | 2021-04-20 |
| 10978576 | Techniques for vertical FET gate length control | Chi-Chun Liu, Chun Wing Yeung, Zhenxing Bi, Kristin Schmidt, Yann Mignot | 2021-04-13 |
| 10955359 | Method for quantification of process non uniformity using model-based metrology | Yunlin Zhang | 2021-03-23 |
| 10930793 | Bottom channel isolation in nanosheet transistors | Choonghyun Lee, Chun Wing Yeung, Jingyun Zhang | 2021-02-23 |
| 10903315 | Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection | Nicolas Loubet, Julien Frougier, Ruilong Xie | 2021-01-26 |
| 10804410 | Bottom channel isolation in nanosheet transistors | Choonghyun Lee, Chun Wing Yeung, Jingyun Zhang | 2020-10-13 |
| 10756178 | Self-limiting and confining epitaxial nucleation | Kangguo Cheng, Nicolas Loubet | 2020-08-25 |
| 10756177 | Self-limiting and confining epitaxial nucleation | Kangguo Cheng, Nicolas Loubet | 2020-08-25 |
| 10741639 | Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection | Nicolas Loubet, Julien Frougier, Ruilong Xie | 2020-08-11 |
| 10692203 | Measuring defectivity by equipping model-less scatterometry with cognitive machine learning | Dexin Kong, Huai Huang | 2020-06-23 |
| 10658459 | Nanosheet transistor with robust source/drain isolation from substrate | Kangguo Cheng, Cheng Chi, Ruilong Xie, John H. Zhang | 2020-05-19 |
| 10636694 | Dielectric isolation in gate-all-around devices | Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie | 2020-04-28 |
| 10553723 | Method for forming doped extension regions in a structure having superimposed nanowires | Remi Coquand, Nicolas Loubet, Shay Reboh | 2020-02-04 |
| 10541239 | Semiconductor device and method of forming the semiconductor device | Hemanth Jagannathan, Choonghyun Lee, Chun Wing Yeung, Jingyun Zhang | 2020-01-21 |
| 10529850 | Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile | Chun Wing Yeung, Choonghyun Lee, Jingyun Zhang, Heng Wu | 2020-01-07 |
| 10475905 | Techniques for vertical FET gate length control | Chi-Chun Liu, Chun Wing Yeung, Zhenxing Bi, Kristin Schmidt, Yann Mignot | 2019-11-12 |
| 10453736 | Dielectric isolation in gate-all-around devices | Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie | 2019-10-22 |