Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11575003 | Creation of stress in the channel of a nanosheet transistor | Nicolas Loubet, Tenko Yamashita, Guillaume Audoit, Nicolas Bernier, Shay Reboh | 2023-02-07 |
| 11515392 | Semiconductor divice having a carbon containing insulation layer formed under the source/drain | Shay Reboh, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang | 2022-11-29 |
| 11450755 | Electronic device including at least one nano-object | Shay Reboh, Emmanuel Augendre, Nicolas Loubet | 2022-09-20 |
| 11177371 | Transistor with superposed bars and double-gate structure | Shay Reboh | 2021-11-16 |
| 11088247 | Method of fabrication of a semiconductor device including one or more nanostructures | Shay Reboh, Kangguo Cheng, Nicolas Loubet | 2021-08-10 |
| 11081547 | Method for making superimposed transistors | Shay Reboh, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang | 2021-08-03 |
| 11049933 | Creation of stress in the channel of a nanosheet transistor | Nicolas Loubet, Tenko Yamashita, Guillaume Audoit, Nicolas Bernier, Shay Reboh | 2021-06-29 |
| 10896956 | Field effect transistor with reduced contact resistance | Shay Reboh | 2021-01-19 |
| 10818775 | Method for fabricating a field-effect transistor | Shay Reboh, Emmanuel Augendre, Nicolas Loubet | 2020-10-27 |
| 10727320 | Method of manufacturing at least one field effect transistor having epitaxially grown electrodes | Shay Reboh, Emmanuel Augendre, Nicolas Loubet | 2020-07-28 |
| 10714392 | Optimizing junctions of gate all around structures with channel pull back | Nicolas Loubet, Emmanuel Augendre, Shay Reboh | 2020-07-14 |
| 10553723 | Method for forming doped extension regions in a structure having superimposed nanowires | Nicolas Loubet, Shay Reboh, Robin Hsin Kuo Chao | 2020-02-04 |
| 10431683 | Method for making a semiconductor device with a compressive stressed channel | Shay Reboh, Emmanuel Augendre, Nicolas Loubet | 2019-10-01 |
| 10269930 | Method for producing a semiconductor device with self-aligned internal spacers | Shay Reboh, Emmanuel Augendre | 2019-04-23 |
| 10263077 | Method of fabricating a FET transistor having a strained channel | Shay Reboh | 2019-04-16 |
| 10256102 | Method for fabricating a field effect transistor having a surrounding grid | Emmanuel Augendre, Shay Reboh | 2019-04-09 |
| 10217849 | Method for making a semiconductor device with nanowire and aligned external and internal spacers | Sylvain Barraud, Emmanuel Augendre, Shay Reboh | 2019-02-26 |
| 10217842 | Method for making a semiconductor device with self-aligned inner spacers | Shay Reboh, Emmanuel Augendre | 2019-02-26 |
| 10147788 | Process for fabricating a field effect transistor having a coating gate | Emmanuel Augendre, Shay Reboh | 2018-12-04 |
| 10141424 | Method of producing a channel structure formed from a plurality of strained semiconductor bars | Emmanuel Augendre, Nicolas Loubet, Shay Reboh | 2018-11-27 |
| 10134875 | Method for fabricating a transistor having a vertical channel having nano layers | Shay Reboh, Emmanuel Augendre | 2018-11-20 |
| 10109735 | Process for fabricating a field effect transistor having a coating gate | Emmanuel Augendre, Shay Reboh | 2018-10-23 |
| 10096694 | Process for fabricating a vertical-channel nanolayer transistor | Emmanuel Augendre, Shay Reboh | 2018-10-09 |