Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12389644 | Method for manufacturing a transistor with a gate-all-around structure | Cyrille Le Royer, Joël KANYANDEKWE | 2025-08-12 |
| 12342617 | Microelectronic device with two field-effect transistors | Joris LACORD | 2025-06-24 |
| 12272398 | Three-dimensional structure of memories for in-memory computing | Théophile Dubreuil, Paul Amari | 2025-04-08 |
| 12237330 | Architecture with stacked N and P transistors with a channel structure formed of nanowires | Jean-Pierre Colinge, Bernard Previtali | 2025-02-25 |
| 11889704 | Device comprising wrap-gate transistors and method of manufacturing such a device | Francois Andrieu | 2024-01-30 |
| 11532670 | 3D memory and manufacturing process | Francois Andrieu | 2022-12-20 |
| 11398593 | Method for producing an electronic component with double quantum dots | Louis HUTIN, Maud Vinet | 2022-07-26 |
| 11239374 | Method of fabricating a field effect transistor | Joris LACORD | 2022-02-01 |
| 11152360 | Architecture of N and P transistors superposed with canal structure formed of nanowires | Jean-Pierre Colinge, Bernard Previtali | 2021-10-19 |
| 11088259 | Method of manufacturing an electronic component including multiple quantum dots | Louis HUTIN, Benoit Patrick Bertrand, Maud Vinet | 2021-08-10 |
| 10903349 | Electronic component with multiple quantum islands | Louis HUTIN, Benoit Patrick Bertrand, Maud Vinet | 2021-01-26 |
| 10522669 | Quantum box device comprising dopants located in a thin semiconductor layer | — | 2019-12-31 |
| 10217849 | Method for making a semiconductor device with nanowire and aligned external and internal spacers | Emmanuel Augendre, Remi Coquand, Shay Reboh | 2019-02-26 |
| 9911841 | Single-electron transistor and its fabrication method | Ivan Duchemin, Louis HUTIN, Yann-Michel Niquet, Maud Vinet | 2018-03-06 |
| 9876121 | Method for making a transistor in a stack of superimposed semiconductor layers | Shay Reboh, Maud Vinet | 2018-01-23 |
| 9853124 | Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers | Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme | 2017-12-26 |
| 9728405 | Nanowire semiconductor device partially surrounded by a gate | Pierrette Rivallin, Pascal Scheiblin | 2017-08-08 |
| 9425255 | Nanowire and planar transistors co-integrated on utbox SOI substrate | Yves Morand | 2016-08-23 |
| 9276073 | Nanowire and planar transistors co-integrated on utbox SOI substrate | Yves Morand | 2016-03-01 |
| 8969148 | Method for producing a transistor structure with superimposed nanowires and with a surrounding gate | Maud Vinet, Laurent Grenouillet | 2015-03-03 |