Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12119258 | Semiconductor structure comprising a buried porous layer for RF applications | Frederic Gaillard, Thomas Lorne, Emmanuel Rolland, Christelle Veytizou, Isabelle Bertrand +1 more | 2024-10-15 |
| 11848191 | RF substrate structure and method of production | Shay Reboh, Pablo Acosta Alba, Thomas Lorne, Emmanuel Rolland | 2023-12-19 |
| 11688811 | Transistor comprising a channel placed under shear strain and fabrication process | Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron | 2023-06-27 |
| 11469137 | Manufacturing process of an RF-SOI trapping layer substrate resulting from a crystalline transformation of a buried layer | Shay Reboh, Pablo Acosta Alba | 2022-10-11 |
| 11450755 | Electronic device including at least one nano-object | Shay Reboh, Remi Coquand, Nicolas Loubet | 2022-09-20 |
| 10978594 | Transistor comprising a channel placed under shear strain and fabrication process | Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron | 2021-04-13 |
| 10818775 | Method for fabricating a field-effect transistor | Shay Reboh, Remi Coquand, Nicolas Loubet | 2020-10-27 |
| 10727320 | Method of manufacturing at least one field effect transistor having epitaxially grown electrodes | Shay Reboh, Remi Coquand, Nicolas Loubet | 2020-07-28 |
| 10714392 | Optimizing junctions of gate all around structures with channel pull back | Nicolas Loubet, Remi Coquand, Shay Reboh | 2020-07-14 |
| 10665497 | Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions | Nicolas Loubet, Sylvain Maitrejean, Pierre Morin | 2020-05-26 |
| 10600786 | Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor | Sylvain Maitrejean, Pierre Morin, Shay Reboh | 2020-03-24 |
| 10431683 | Method for making a semiconductor device with a compressive stressed channel | Shay Reboh, Remi Coquand, Nicolas Loubet | 2019-10-01 |
| 10269930 | Method for producing a semiconductor device with self-aligned internal spacers | Shay Reboh, Remi Coquand | 2019-04-23 |
| 10256102 | Method for fabricating a field effect transistor having a surrounding grid | Remi Coquand, Shay Reboh | 2019-04-09 |
| 10217849 | Method for making a semiconductor device with nanowire and aligned external and internal spacers | Sylvain Barraud, Remi Coquand, Shay Reboh | 2019-02-26 |
| 10217842 | Method for making a semiconductor device with self-aligned inner spacers | Shay Reboh, Remi Coquand | 2019-02-26 |
| 10147788 | Process for fabricating a field effect transistor having a coating gate | Remi Coquand, Shay Reboh | 2018-12-04 |
| 10141424 | Method of producing a channel structure formed from a plurality of strained semiconductor bars | Remi Coquand, Nicolas Loubet, Shay Reboh | 2018-11-27 |
| 10134875 | Method for fabricating a transistor having a vertical channel having nano layers | Shay Reboh, Remi Coquand | 2018-11-20 |
| 10109735 | Process for fabricating a field effect transistor having a coating gate | Remi Coquand, Shay Reboh | 2018-10-23 |
| 10096694 | Process for fabricating a vertical-channel nanolayer transistor | Remi Coquand, Shay Reboh | 2018-10-09 |
| 9997394 | Method for transferring a thin layer with supply of heat energy to a fragile zone via an inductive layer | Thomas Signamarcheix, Lamine Benaissa | 2018-06-12 |
| 9917153 | Method for producing a microelectronic device | Thierry Baron | 2018-03-13 |
| 9853124 | Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers | Sylvain Barraud, Sylvain Maitrejean, Nicolas Posseme | 2017-12-26 |
| 9853130 | Method of modifying the strain state of a semiconducting structure with stacked transistor channels | Sylvain Maitrejean, Jean-Charles Barbe, Benoit Mathieu, Yves Morand | 2017-12-26 |