Issued Patents All Time
Showing 1–25 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12363918 | Method for co-manufacturing a ferroelectric memory and an OxRAM resistive memory and device co-integrating a ferroelectric memory and an OxRAM resistive memory | Jean Coignus, Elisa VIANELLO | 2025-07-15 |
| 12215430 | Method for increasing the surface roughness of a metal layer | Nicolas Posseme, Olivier Pollet | 2025-02-04 |
| 12094722 | Method for increasing the surface roughness of a metal layer | Olivier Pollet, Nicolas Posseme | 2024-09-17 |
| 12033696 | Memory circuit comprising a plurality of 1T1R memory cells | Olivier Billoint, Carlo Cagli | 2024-07-09 |
| 11944022 | Resistive memory with a switching zone between two dielectric regions having different doping and/or dielectric constants | Marios Barlas, Etienne Nowak | 2024-03-26 |
| 11887662 | Matrix of elementary switches forming a message, associated reading and writing methods | Anthonin Verdy | 2024-01-30 |
| 11264479 | Process for producing FET transistors | Maud Vinet, Romain Wacquez | 2022-03-01 |
| 11189792 | Oxide-based resistive non-volatile memory cell and method for manufacturing same | Marios Barlas, Philippe Blaise, Benoit Sklenard, Elisa VIANELLO | 2021-11-30 |
| 11145663 | Method for fabricating a ferroelectric memory and method for co-fabrication of a ferroelectric memory and of a resistive memory | Christelle Charpin-Nicolle, Jean Coignus, Terry Francois, Sebastien Kerdiles | 2021-10-12 |
| 10985317 | Device for selecting a memory cell | Marios Barlas, Philippe Blaise, Benoit Sklenard, Elisa VIANELLO | 2021-04-20 |
| 10777701 | Photosensitive detector with self-aligned 3D junction and gate | Lina Kadura, Olivier Rozeau, Alexei Tchelnokov | 2020-09-15 |
| 10453960 | Transistor having structured source and drain regions and production method thereof | Vincent Mazzocchi | 2019-10-22 |
| 10446564 | Non-volatile memory allowing a high integration density | Jean-Michel PORTAL, Marios Barlas, Elisa VIANELLO | 2019-10-15 |
| 10347545 | Method for producing on the same transistors substrate having different characteristics | Sebastien Barnola, Marie-Anne Jaud, Jerome Mazurier, Nicolas Posseme | 2019-07-09 |
| 10347721 | Method to increase strain in a semiconductor region for forming a channel of the transistor | Shay Reboh, Raluca Tiron | 2019-07-09 |
| 10290667 | Front-illuminated photosensitive logic cell | Olivier Rozeau | 2019-05-14 |
| 10026657 | Method for producing on the same transistors substrate having different characteristics | Nicolas Posseme | 2018-07-17 |
| 10014183 | Method for patterning a thin film | Shay Reboh, Yves Morand | 2018-07-03 |
| 9935019 | Method of fabricating a transistor channel structure with uniaxial strain | Shay Reboh, Frederic Milesi, Yves Morand, Francois Rieutord | 2018-04-03 |
| 9911820 | Method for fabrication of a field-effect with reduced stray capacitance | Cyrille Le Royer, Frederic Boeuf, Louis HUTIN, Yves Morand | 2018-03-06 |
| 9841657 | CMOS photonic inverter | Olivier Rozeau | 2017-12-12 |
| 9831288 | Integrated circuit cointegrating a FET transistor and a RRAM memory point | Sotirios Athanasiou, Philippe Galy | 2017-11-28 |
| 9711567 | Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location | Yves Morand, Maud Vinet | 2017-07-18 |
| 9673329 | Method for manufacturing a fin MOS transistor | Yves Morand, Romain Wacquez, Yannick Le Tiec, Maud Vinet | 2017-06-06 |
| 9634103 | CMOS in situ doped flow with independently tunable spacer thickness | Maud Vinet, Qing Liu | 2017-04-25 |