Issued Patents All Time
Showing 1–25 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12336261 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Chun-Hsiung Lin +2 more | 2025-06-17 |
| 12237330 | Architecture with stacked N and P transistors with a channel structure formed of nanowires | Sylvain Barraud, Bernard Previtali | 2025-02-25 |
| 12148816 | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same | Carlos H. Diaz, Yee-Chia Yeo | 2024-11-19 |
| 11990532 | Method of forming transistor | Carlos H. Diaz | 2024-05-21 |
| 11961892 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Chun-Hsiung Lin +2 more | 2024-04-16 |
| 11929417 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Chun-Hsiung Lin +2 more | 2024-03-12 |
| 11875935 | Integrated electronic device comprising a coil and method for manufacturing such a device | — | 2024-01-16 |
| 11854905 | Silicon and silicon germanium nanowire formation | Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz | 2023-12-26 |
| 11777009 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Chun-Hsiung Lin +2 more | 2023-10-03 |
| 11646219 | Manufacturing process of a structured substrate | — | 2023-05-09 |
| 11557532 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Ta-Pen Guo, Carlos H. Diaz, Yi-Hsiung Lin | 2023-01-17 |
| 11532727 | Method of forming transistor | Carlos H. Diaz | 2022-12-20 |
| 11532705 | 3D cross-bar nonvolatile memory | Carlos H. Diaz, Ta-Pen Guo | 2022-12-20 |
| 11404325 | Silicon and silicon germanium nanowire formation | Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz | 2022-08-02 |
| 11362051 | RF substrate with junctions having an improved layout | Louis HUTIN, Maxime MOULIN, Thibaud FACHE | 2022-06-14 |
| 11302804 | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same | Carlos H. Diaz, Yee-Chia Yeo | 2022-04-12 |
| 11276763 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Chun-Hsiung Lin +2 more | 2022-03-15 |
| 11239347 | Method for making a transistor of which the active region includes a semimetal material | Yves Morand | 2022-02-01 |
| 11239084 | Semiconductor device and manufacturing method thereof | Carlos H. Diaz | 2022-02-01 |
| 11227800 | Method for producing transistors implemented at low temperature | — | 2022-01-18 |
| 11152360 | Architecture of N and P transistors superposed with canal structure formed of nanowires | Sylvain Barraud, Bernard Previtali | 2021-10-19 |
| 11133404 | FinFET device including a stem region of a fin element | Kuo-Cheng Ching, Zhiqiang Wu | 2021-09-28 |
| 11127734 | Vertical nanowire transistor for input/output structure | Ta-Pen Guo, Carlos H. Diaz | 2021-09-21 |
| 11104573 | Semiconductor arrangement with one or more semiconductor columns | Ta-Pen Guo, Chih-Hao Wang, Carlos H. Diaz | 2021-08-31 |
| 11043597 | Method for reducing contact resistance in semiconductor structures | Carlos H. Diaz | 2021-06-22 |