Issued Patents All Time
Showing 51–75 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10325989 | Semiconductor device with silicide | Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz | 2019-06-18 |
| 10294101 | Semiconductor arrangement with one or more semiconductor columns | Ta-Pen Guo, Chih-Hao Wang, Carlos H. Diaz | 2019-05-21 |
| 10290737 | Semiconductor arrangement with one or more semiconductor columns | Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz | 2019-05-14 |
| 10276664 | Semiconductor structures and methods for multi-dimension of nanowire diameter to improve drive current | Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu | 2019-04-30 |
| 10269572 | Semiconductor device and manufacturing method thereof | Carlos H. Diaz | 2019-04-23 |
| 10193090 | Method of manufacturing a semiconductor device and a semiconductor device | Chun-Chieh Lu, Ken-Ichi Goto, Zhiqiang Wu, Yu-Ming Lin | 2019-01-29 |
| 10191694 | 3D cross-bar nonvolatile memory | Carlos H. Diaz, Ta-Pen Guo | 2019-01-29 |
| 10170404 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Ta-Pen Guo, Carlos H. Diaz, Yi-Hsiung Lin | 2019-01-01 |
| 10164040 | Gate structure and method for fabricating the same | Ta-Pen Guo, Carlos H. Diaz | 2018-12-25 |
| 10164061 | Method of fabricating non-volatile memory device array | Carlos H. Diaz | 2018-12-25 |
| 10164105 | Forming conductive STI liners for FinFETs | — | 2018-12-25 |
| 10163729 | Silicon and silicon germanium nanowire formation | Kuo-Cheng Ching, Carlos H. Diaz | 2018-12-25 |
| 10157928 | Semiconductor devices and methods of manufacture thereof | Carlos H. Diaz, Ta-Pen Guo | 2018-12-18 |
| 10134918 | Memory device and method for fabricating the same | Ta-Pen Guo, Carlos H. Diaz | 2018-11-20 |
| 10134915 | 2-D material transistor with vertical structure | Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Ken-Ichi Goto, Ta-Pen Guo +3 more | 2018-11-20 |
| 10083869 | Stacked device and associated layout structure | Ta-Pen Guo, Carlos H. Diaz, Chih-Hao Wang | 2018-09-25 |
| 10062779 | Semiconductor device and manufacturing method thereof | Carlos H. Diaz | 2018-08-28 |
| 10026826 | Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric | Carlos H. Diaz, Yeh Hsu, Tsung-Hsing Yu, Chia-Wen Liu | 2018-07-17 |
| 10008566 | Semiconductor device with reduced electrical resistance and capacitance | Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz | 2018-06-26 |
| 10008253 | Array architecture and write operations of thyristor based random access memory | Yue-Der Chih, Carlos H. Diaz, Jonathan Tsung-Yung Chang | 2018-06-26 |
| 10002922 | Process to etch semiconductor materials | Carlos H. Diaz, Mark van Dal | 2018-06-19 |
| 9978863 | Semiconductor arrangement with one or more semiconductor columns | Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz | 2018-05-22 |
| 9941404 | Tuning strain in semiconductor devices | Kuo-Cheng Ching, Gwan Sin Chang, Zhiqiang Wu, Chih-Hao Wang, Carlos H. Diaz | 2018-04-10 |
| 9941374 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Chun-Hsiung Lin +2 more | 2018-04-10 |
| 9935198 | Method for inducing strain in vertical semiconductor columns | Gwan Sin Chang, Carlos H. Diaz | 2018-04-03 |