Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11804546 | Structure and method for integrated circuit | Shin-Jiun Kuang, Yi-Ming Sheu | 2023-10-31 |
| 11715785 | Semiconductor device and manufacturing method thereof | Shin-Jiun Kuang, Yi-Han Wang, Yi-Ming Sheu | 2023-08-01 |
| 11502198 | Structure and method for integrated circuit | Shin-Jiun Kuang, Yi-Ming Sheu | 2022-11-15 |
| 11004955 | Semiconductor device and manufacturing method thereof | Shin-Jiun Kuang, Yi-Han Wang, Yi-Ming Sheu | 2021-05-11 |
| 10868175 | Method for manufacturing semiconductor structure | Shin-Jiun Kuang, Yi-Ming Sheu | 2020-12-15 |
| 10741688 | Structure and method for integrated circuit | Shin-Jiun Kuang, Yi-Ming Sheu | 2020-08-11 |
| 10734503 | Asymmetric semiconductor device | Jean-Pierre Colinge, Carlos H. Diaz, Yeh Hsu, Chia-Wen Liu | 2020-08-04 |
| 10522657 | Semiconductor device and manufacturing method thereof | Shin-Jiun Kuang, Yi-Han Wang, Yi-Ming Sheu | 2019-12-31 |
| 10276664 | Semiconductor structures and methods for multi-dimension of nanowire diameter to improve drive current | Chia-Wen Liu, Yeh Hsu, Jean-Pierre Colinge | 2019-04-30 |
| 10084063 | Semiconductor device and manufacturing method thereof | Shin-Jiun Kuang, Yi-Han Wang, Yi-Ming Sheu | 2018-09-25 |
| 10026826 | Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric | Jean-Pierre Colinge, Carlos H. Diaz, Yeh Hsu, Chia-Wen Liu | 2018-07-17 |
| 9899475 | Epitaxial channel with a counter-halo implant to improve analog gain | Shih-Syuan Huang, Ken-Ichi Goto, Yi-Ming Sheu | 2018-02-20 |
| 9899517 | Dislocation stress memorization technique (DSMT) on epitaxial channel devices | Shih-Syuan Huang, Yi-Ming Sheu, Ken-Ichi Goto | 2018-02-20 |
| 9893183 | Semiconductor structure and manufacturing method thereof | Shin-Jiun Kuang, Yi-Ming Sheu | 2018-02-13 |
| 9837533 | Semiconductor structure and manufacturing method thereof | Shin-Jiun Kuang, Yi-Ming Sheu, Chun-Yi Lee, Chia-Wen Liu | 2017-12-05 |
| 9831341 | Structure and method for integrated circuit | Shin-Jiun Kuang, Yi-Ming Sheu | 2017-11-28 |
| 9768297 | Process design to improve transistor variations and performance | Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu | 2017-09-19 |
| 9728602 | Variable channel strain of nanowire transistors to improve drive current | Yeh Hsu, Chia-Wen Liu, Jean-Pierre Colinge | 2017-08-08 |
| 9716172 | Semiconductor device having multiple active area layers and its formation thereof | Chia-Wen Liu, Yeh Hsu, Ken-Ichi Goto | 2017-07-25 |
| 9660049 | Semiconductor transistor device with dopant profile | Chia-Wen Liu, Ken-Ichi Goto | 2017-05-23 |
| 9653545 | MOSFET structure with T-shaped epitaxial silicon channel | Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto +1 more | 2017-05-16 |
| 9634132 | Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current | Chia-Wen Liu, Yeh Hsu, Jean-Pierre Colinge | 2017-04-25 |
| 9620591 | Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current | Yeh Hsu, Chia-Wen Liu, Jean-Pierre Colinge | 2017-04-11 |
| 9553150 | Transistor design | Wen-Yuan Chen, Ken-Ichi Goto, Zhiqiang Wu | 2017-01-24 |
| 9536746 | Recess and epitaxial layer to improve transistor performance | Yeh Hsu, Chia-Wen Liu, Ken-Ichi Goto, Shih-Syuan Huang | 2017-01-03 |