Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426292 | Semiconductor device with tunable threshold voltage and method for manufacturing the same | Chansyun David Yang, Huang-Lin Chao, Hsiang-Pi Chang, Yen-Tien Tung, Chung-Liang Cheng +4 more | 2025-09-23 |
| 12382691 | Effective work function tuning via silicide induced interface dipole modulation for metal gates | Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang +3 more | 2025-08-05 |
| 12300721 | Semiconductor device structure with channel and method for forming the same | Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Zhiqiang Wu | 2025-05-13 |
| 12302640 | Integrated circuit structure and method with hybrid orientation for FinFET | Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang +1 more | 2025-05-13 |
| 12288722 | Spacer structure for semiconductor device and method for forming the same | Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Fu-Ting Yen, Gary Chan +3 more | 2025-04-29 |
| 12289893 | Semiconductor devices including FTJ structure | Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong +4 more | 2025-04-29 |
| 12218205 | 2D-channel transistor structure with source-drain engineering | Dhanyakumar Mahaveer Sathaiya, Khaderbad Mrunal Abhijith | 2025-02-04 |
| 12166074 | Gate structure in semiconductor device and method of forming the same | Hsin-Yi Lee, Weng Chang, Hsiang-Pi Chang, Huang-Lin Chao, Chung-Liang Cheng +4 more | 2024-12-10 |
| 12136570 | Graphene layer for low resistance contacts and damascene interconnects | Mrunal A. Khaderbad, Wei-Yen Woon, Cheng-Ming Lin, Han-Yu Lin, Szu-Hua Chen +1 more | 2024-11-05 |
| 12087819 | Dual channel structure | Mrunal A. Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin | 2024-09-10 |
| 12040372 | Contact structures in semiconductor devices | Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Shuen-Shin Liang +2 more | 2024-07-16 |
| 11990522 | Effective work function tuning via silicide induced interface dipole modulation for metal gates | Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang +3 more | 2024-05-21 |
| 11942134 | Memory circuit and write method | Huan-Sheng Wei, Zhiqiang Wu | 2024-03-26 |
| 11894461 | Dipoles in semiconductor devices | Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang +2 more | 2024-02-06 |
| 11855192 | Semiconductor device and manufacturing method thereof | Han-Yu Lin, Fang-Wei Lee, Kai Tak Lam, Raghunath PUTIKAM, Li-Te Lin +4 more | 2023-12-26 |
| 11843032 | Semiconductor device structure with channel and method for forming the same | Huang-Siang LAN, Sathaiya Mahaveer DHANYAKUMAR, Zhiqiang Wu | 2023-12-12 |
| 11810960 | Contact structures in semiconductor devices | Sung-Li Wang, Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu +1 more | 2023-11-07 |
| 11735594 | Integrated circuit structure and method with hybrid orientation for FinFET | Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang +1 more | 2023-08-22 |
| 11728391 | 2d-channel transistor structure with source-drain engineering | Dhanyakumar Mahaveer Sathaiya, Khaderbad Mrunal Abhijith | 2023-08-15 |
| 11545397 | Spacer structure for semiconductor device and method for forming the same | Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Fu-Ting Yen, Gary Chan +3 more | 2023-01-03 |
| 11527622 | Effective work function tuning via silicide induced interface dipole modulation for metal gates | Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang +3 more | 2022-12-13 |
| 11508427 | Memory circuit and write method | Huan-Sheng Wei, Zhiqiang Wu | 2022-11-22 |
| 11489057 | Contact structures in semiconductor devices | Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Shuen-Shin Liang +2 more | 2022-11-01 |
| 11476333 | Dual channel structure | Mrunal A. Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin | 2022-10-18 |
| 11031418 | Integrated circuit structure and method with hybrid orientation for FinFET | Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang +1 more | 2021-06-08 |